AMD 12 core 24 thread Zen2 engineering sample benchmark leaked

[leadeater]

17 minutes ago, porina said:

 I'm making the assumption that they are only using 6 out of 8 potential cores but not disabling cache. The other possibility is they are doing 2.66MB/core which would be an odd number.

L3 cache should be the same as it's per CCX and shared across the cores, I think some existing Zen had some of it disabled but others of the same count counts did not. I'm not 100% sure on that because from memory AMD said on the higher desktop parts they did not disable a CCX for any of the 4 core parts which is where that comes in to interest. The 1200-1400 has 8MB L3 cache and the 1500X has 16MB L3 cache, all 4 core parts. A disabled CCX would explain the 8MB vs 16MB but that's not supposed to be a thing?

 

 

[Lawliet93]

It definitely does not have a disabled CCX, any core count would be made in a linear fashion. So  for a 12c CPU it means, that they are using two six-core dies. It also makes more sense in terms of yields. Using defective dies for such a multi chip approach reduces costs in the long run. And they can be binned for speed, so we shouldn't sacrifice singlethreaded performance. 

[Mihle]

22 minutes ago, Lawliet93 said:

It definitely does not have a disabled CCX, any core count would be made in a linear fashion. So  for a 12c CPU it means, that they are using two six-core dies. It also makes more sense in terms of yields. Using defective dies for such a multi chip approach reduces costs in the long run. And they can be binned for speed, so we shouldn't sacrifice singlethreaded performance. 

It is technically possible for the 12 core to have higher clock speed than the 8 core that just has one core chip.

[Carclis]

4 hours ago, Rauten said:

TR2 2920X is a Zen+ 12/24 at 3.5Ghz base and 4.3Ghz boost

So logic dictates that with the 7nm process and the Zen2 improvements, those speeds should be quite far from final. It maybe not reach the leaked 4.2/5.0 speeds, but they should be higher than both this benchmark and the 2920x.

TR2 is also 180W compared to this 105W chip. So assuming the whole of those 7nm improvements went towards 50% power at the same clocks then this would be about in line with what you'd expect (barring whatever overhead quad channel memory would add to the power numbers).

[Rauten]

22 minutes ago, Carclis said:

TR2 is also 180W compared to this 105W chip. So assuming the whole of those 7nm improvements went towards 50% power at the same clocks then this would be about in line with what you'd expect (barring whatever overhead quad channel memory would add to the power numbers).

True, completely forgot the TDP.

Anandtech checked the actual power draw for TR2 and found that the 2920X draws 148W to power all 12 cores and just the cores, with an additional 30W for IO, DRAM, Infinity Fabric and whatnot.

So yeah, either the clocks won't be anywhere near the leak or Zen2 has some "sekrit sauce" going on to lower power consumption.

[leadeater]

6 minutes ago, Rauten said:

So yeah, either the clocks won't be anywhere near the leak or Zen2 has some "sekrit sauce" going on to lower power consumption.

Zen2 is on 7nm node compared to current 12nm(really 14nm optimized) and 14nm. I'm not exactly expecting 5Ghz like the silly rumors but Zen2 at same core count and frequencies will use some decent ish amount less power.

 

Take that 2920X, 110W-120W maybe on Zen2.

[Lurick]

13 hours ago, S w a t s o n said:

head room for sure on these numbers, you think the chips will really only do 3.6ghz?

I definitely think there is head room and that it will probably do 4GHz easily but the hyped up 5GHz crap I've seen just kind of irritates me =/

[S w a t s o n]

11 minutes ago, Lurick said:

I definitely think there is head room and that it will probably do 4GHz easily but the hyped up 5GHz crap I've seen just kind of irritates me =/

Oh god they will definitely do over 4ghz. Remember that 12 cores at 4ghz is starting to become a heat problem for stock coolers. They probably wont release one that boosts to 5ghz (excep thalo product) due to that. These chips should do zen+ clocks minimum

[cj09beira]

On 1/25/2019 at 3:24 AM, leadeater said:

L3 cache should be the same as it's per CCX and shared across the cores, I think some existing Zen had some of it disabled but others of the same count counts did not. I'm not 100% sure on that because from memory AMD said on the higher desktop parts they did not disable a CCX for any of the 4 core parts which is where that comes in to interest. The 1200-1400 has 8MB L3 cache and the 1500X has 16MB L3 cache, all 4 core parts. A disabled CCX would explain the 8MB vs 16MB but that's not supposed to be a thing?

they have the ability to disable half the cache from a single ccx, thats how they do it

 

On 1/25/2019 at 7:12 AM, Lurick said:

I definitely think there is head room and that it will probably do 4GHz easily but the hyped up 5GHz crap I've seen just kind of irritates me =/

all core boost doesn't affect single core boost, that will be determined by how good the node is up top as long as the design doesn't become the bottleneck

[Fasauceome]

3 hours ago, Rauten said:

So yeah, either the clocks won't be anywhere near the leak or Zen2 has some "sekrit sauce" going on to lower power consumption.

The cinebench demo at 30% less power consumption of the i9 9900k side by side seems to indicate a pretty decent helping of sekrit sauce, unless AMD literally just outright lied during the presentation about the configuration. 

[schwellmo92]

 

4 hours ago, Rauten said:

True, completely forgot the TDP.

Anandtech checked the actual power draw for TR2 and found that the 2920X draws 148W to power all 12 cores and just the cores, with an additional 30W for IO, DRAM, Infinity Fabric and whatnot.

So yeah, either the clocks won't be anywhere near the leak or Zen2 has some "sekrit sauce" going on to lower power consumption.

If we look at a 1920X, its TDP is 180w for 3.5GHz base and 4GHz boost (4.2GHz on up to 4 cores with XFR - 3.7GHz all-core boost). If we follow the above calculations and assume that it took 30w for non-core related tasks which leave 150w power draw for the cores, with 14nm > 7nm we half the power draw and we get 75w for the cores + 30w for the non-core related (assuming that doesn't change) we get 105w. So in theory you could still get a 12c/24t Zen 2 chip with 105w at 3.7GHz base/all-core, and I would just expect the turbo to be more aggressive and drop off quicker as more cores come under load. For reference a 9900K does 4.2GHz when at its 95w TDP.

[The Benjamins]

4 hours ago, Rauten said:

True, completely forgot the TDP.

Anandtech checked the actual power draw for TR2 and found that the 2920X draws 148W to power all 12 cores and just the cores, with an additional 30W for IO, DRAM, Infinity Fabric and whatnot.

So yeah, either the clocks won't be anywhere near the leak or Zen2 has some "sekrit sauce" going on to lower power consumption.

Its called 7nm, they gain 50% power efficiency, the 8 core part demoed was a 50-65w part, that leavels plenty of room for 4 more cores at the same clocks (power budget wise)

[Doobeedoo]

We know they can fit more cores, seeing the dies and 7nm benefits. For AM4 getting more cores would be quite awesome actually. 

Can't wait to see how much clocks can be pushed on new series. 

[CarlBar]

3 hours ago, The Benjamins said:

Its called 7nm, they gain 50% power efficiency, the 8 core part demoed was a 50-65w part, that leaves plenty of room for 4 more cores at the same clocks (power budget wise)

 

Yeah i had some serious doubts about the power numbers when the leaks hit initially but unless we assume AMD where majorly lying they have quite a bit of headroom in a 105w budget to add 50% more cores at the same clocks. And that was early silicon too. The IO die is probably the main thing subject to change but a CPU die revision as they get more familiar with the 7nm process and what they can tweak isn't unreasonable in the slightest. And the IO die undoubtedly puts some limits in the CPU die thermals too as if thats still a bit buggy it may very well not be doing as god a job of managing the workload efficiently.

[Trixanity]

I'm quite sure the first original Zen leaks had samples running at 3 GHz and everyone was saying AMD had messed up and was gonna go bankrupt with another failure aka Bulldozer 2.0. Just saying.

[cj09beira]

@Taf the Ghost @leadeater

we just got zen 2's latency diagram, slightly better up to 16mb, worse after that, 

[Taf the Ghost]

4 minutes ago, cj09beira said:

@Taf the Ghost @leadeater

we just got zen 2's latency diagram, slightly better up to 16mb, worse after that, 

It's 16 mb per CCX. The main thing is that we now are sure it's still 4c CCX setups. It'll be interesting to see the cross-CCX latency & speeds. Zen1 was fun for all of the new dynamics it brought it, but Zen2 with full chiplets is going to be really interesting. 

 

One thing I hadn't thought of until recently is that as DDR4 increases in baseline speed, and especially with DDR5 on the horizon, the 1:2 IF speed will be less of an issue. I think that latency weakness might go away with successive generations simply from the latency drop in the IF as it improves. We know the Ring Bus has a pretty tight core & bandwidth range before the latency advantage drops off, which is why the modern server parts use the Mesh. Be something interesting to watch.

[cj09beira]

just hope they are running something like 2400 cl17 on that test, hopefully it can at least match zen 1 with proper ram

[Taf the Ghost]

14 hours ago, cj09beira said:

just hope they are running something like 2400 cl17 on that test, hopefully it can at least match zen 1 with proper ram

Considering what the early vs recent BIOS did for Zen1, there's going to be some room. Also, they already moved to 2933 as being baseline supported memory, so there's a good chance it's going to be 3200 for Zen2 parts. That'll matter a lot to certain workloads.

 

The really interesting part to watch is what interesting results come from separating the IMC and CPU cores again, with a modern design. It's going to be fun, either way.

 

One other thing to note, which a few people caught on to, but AMD is clearly sandbagging on their ES models for clocks. The stage demonstration at CES had to be running the 4 Ghz all-core range, and the first 12c model SKU was boosting to 4 Ghz but the recent ones have been lower. 

 

AMD is kind of taking a reversal approach for leaking information out about Ryzen 3rd gen compared to Rome. Rome info leaked like a sieve; Matisse info is brutally hard to come by.

[cj09beira]

1 minute ago, Taf the Ghost said:

One other thing to note, which a few people caught on to, but AMD is clearly sandbagging on their ES models for clocks. The stage demonstration at CES had to be running the 4 Ghz all-core range, and the first 12c model SKU was boosting to 4 Ghz but the recent ones have been lower. 

 

AMD is kind of taking a reversal approach for leaking information out about Ryzen 3rd gen compared to Rome. Rome info leaked like a sieve; Matisse info is brutally hard to come by.

ya from only showing 8 core chips at CES to low amounts of leaks, amd is trying to WoW everyone one of this days, just a shame we might be waiting for the x570 chipset,

2019 is going to be fun, and even tough i just got myself a 2600, i might need to sell it , hopefully zen 2 plays nicer with 3d mark, my 2600 can just about match my 4690k (@4.6-4.7) on the combined score, (though much higher physics) 

[CarlBar]

1 hour ago, Taf the Ghost said:

It's 16 mb per CCX. The main thing is that we now are sure it's still 4c CCX setups. It'll be interesting to see the cross-CCX latency & speeds. Zen1 was fun for all of the new dynamics it brought it, but Zen2 with full chiplets is going to be really interesting. 

 

One thing I hadn't thought of until recently is that as DDR4 increases in baseline speed, and especially with DDR5 on the horizon, the 1:2 IF speed will be less of an issue. I think that latency weakness might go away with successive generations simply from the latency drop in the IF as it improves. We know the Ring Bus has a pretty tight core & bandwidth range before the latency advantage drops off, which is why the modern server parts use the Mesh. Be something interesting to watch.

 

Care to point to where 4 core CCX's have been confirmed?

[Taf the Ghost]

12 hours ago, cj09beira said:

ya from only showing 8 core chips at CES to low amounts of leaks, amd is trying to WoW everyone one of this days, just a shame we might be waiting for the x570 chipset,

2019 is going to be fun, and even tough i just got myself a 2600, i might need to sell it , hopefully zen 2 plays nicer with 3d mark, my 2600 can just about match my 4690k (@4.6-4.7) on the combined score, (though much higher physics) 

When it comes to Desktop CPUs, I think it's important to remember that AMD actually has significant market share in Retail. It's not exactly reflective of Mindfactory's numbers, but it's between 30-40% of the Retail CPU purchases during any given year. Trending a bit higher with Zen's launch. That's important as AMD is going to be a tad more careful about the press around their launch cycle. They know they've got a special generation coming, so they want to let the supply channel thin out a bit before starting the hype-train.

 

12 hours ago, CarlBar said:

Care to point to where 4 core CCX's have been confirmed?

The UserBench ES' latency numbers. A core has direct access to 16 mb of L3. From the Rome information, we know it's 32 mb of L3 per Chiplet. Ergo, it's two CCX per chiplet. Though it should be noted that the traces on the 1 Chiplet + I/O die parts shown at CES pretty clearly showed the 2x CCX layout. 

 

The interesting question is if there is some sort of cross bar-like IF connection between the two CCX on the same chiplet. Route traversal is going to be a really interesting part about the chiplet design.

[CarlBar]

3 minutes ago, Taf the Ghost said:

The UserBench ES' latency numbers. A core has direct access to 16 mb of L3. From the Rome information, we know it's 32 mb of L3 per Chiplet. Ergo, it's two CCX per chiplet. Though it should be noted that the traces on the 1 Chiplet + I/O die parts shown at CES pretty clearly showed the 2x CCX layout. 

 

The interesting question is if there is some sort of cross bar-like IF connection between the two CCX on the same chiplet. Route traversal is going to be a really interesting part about the chiplet design.

 

Or one part of the cache is slower than the other. AFAIK thats been done before without calling it L4. Also the traces showed nothing of the sort that i can see, it could be 4 coe CCX's or it could be one big set of 8 cores, it's not clear.

[leadeater]

4 hours ago, Taf the Ghost said:

The interesting question is if there is some sort of cross bar-like IF connection between the two CCX on the same chiplet. Route traversal is going to be a really interesting part about the chiplet design.

Um? The CCX's have always used IF for intercommunication. IF itself is broad and has multiple implementations from on die, inter die, inter package to inter device.

[Taf the Ghost]

3 minutes ago, leadeater said:

Um? The CCX's have always used IF for intercommunication. IF itself is broad and has multiple implementations from on die, inter die, inter package to inter device.

Right. For Zen2, are they going to implement the CCX to CCX comms differently?