AMD 12 core 24 thread Zen2 engineering sample benchmark leaked

[leadeater]

3 minutes ago, Taf the Ghost said:

Right. For Zen2, are they going to implement the CCX to CCX comms differently?

Don't know, probably not. Should be stand improvements etc but then I don't know how the chiplet to I/O die would effect it. Probably going to be much like Zen/Zen+ with the memory controller for the whole die and both CCXs shared but instead of it being a memory controller it's an IF link to the I/O die.

[Stefan Payne]

13 hours ago, Taf the Ghost said:

One other thing to note, which a few people caught on to, but AMD is clearly sandbagging on their ES models for clocks. The stage demonstration at CES had to be running the 4 Ghz all-core range,

Its rumored to be around 4,3-4,5GHz.

 

Quote

AMD is kind of taking a reversal approach for leaking information out about Ryzen 3rd gen compared to Rome. Rome info leaked like a sieve; Matisse info is brutally hard to come by.

You have to look at it from the Beginning:

How many people have access to a Rome CPU?
How many people have access to a Mantisse based CPU?

 

And compare that to the leaks.

 

So with Rome we had a ton of leaks. So isn't it safe to assume that a ton of people had access to that CPU?

With Mantisse we have the usual occasional leaks. So isn't it safe to assume that hardly anyone has access to a Mantisse CPU?

 

And now who needs to have a pre production sample of the CPU before it comes to the store?

 

For Rome we have all the Server Manufacturers, maybe even some people. My guess is that a couple of hundred, if not thousand people have access to the Rome Chip for evaluation purposes. And probably even possible future Buyers of the System (ie Microsoft, Amazon for their Cloud Storage Stuff, maybe even Twitter, Facebook, Google. And Probably also every bigger, named University)...

 

For Mantisse, outside of AMD, its the Motherboard Manufacturers for Testing purpose, Optimization. And maybe Dell, HP and co. And that's it. Nobody else probably has a Mantisse CPU.

 

7 hours ago, Taf the Ghost said:

Right. For Zen2, are they going to implement the CCX to CCX comms differently?

We don't know yet if its 1 IF Link per Die or (at least) 2...

That would be the interesting question, if Die0 can Access Die1 without going through the I/O Die.

[Taf the Ghost]

2 minutes ago, Stefan Payne said:

We don't know yet if its 1 IF Link per Die or (at least) 2...

That would be the interesting question, if Die0 can Access Die1 without going through the I/O Die.

Considering the CCX to CCX latency was an issue with Zen1, I'm curious if gen 2 will have more design improvements, or if that only shows up in Zen3 because that's the first time they'll have enough information about Zen1 to really do the tweaking on the design for that specifically. 

[RejZoR]

On 1/25/2019 at 12:28 AM, Lurick said:

But....but.....my 5GHz boost

*eye roll*

 

If people really thought a 12 core/24 thread chip like that was going to magically jump up to 5GHz boost then I've got a few swamps and bridges to sell. People got their hopes way too high due to one or two news outlets hyping up a bunch of BS and now people are going to turn their anger to AMD directly because leaks by other people are going to somehow be AMD's fault.

 

For the record, I think AMD has done an awesome job with Ryzen and hopefully pushes things further with Ryzen 2, I'm just tried of all this smoke being blown about some magic chip that's going to save us from the darks of Intel. I'll wait for benchmarks but I could see it being that AMD might not even need to hit anywhere near a 5GHz boost to give Intel even more run for their money and I hope they keep pushing because I want them to make Intel sweat hard.

And why would that be something impossible? Who honestly expects all 12 cores to run at 5GHz? 2700X didn't run 4.3GHz on all cores out of the box either. It had rolloff design. It ran at 4.3GHz when only 4 cores were loaded. When more cores got loaded, the clocks started dropping. So, how is 5GHz on lets say 4 cores unrealistic and then dropping as you start using more cores? It's exactly what Intel is doing as well.

 

I'm hyped for it having 5GHz, but I won't be disappointed if it won't. It just means I'll stick with my 5820K for some time longer then as I have plenty threads already (12) and clock is also reasonably high (4.5GHz) so my only real gain is having higher clock. If new CPU's won't have it I simply won't upgrade yet. And that's that. A bit of a shame since I'd like to jump on AMD side again, but with 4.3GHz (or 3.6GHz) I'm actually gaining very little despite IPC improvements.

[leadeater]

28 minutes ago, Stefan Payne said:

That would be the interesting question, if Die0 can Access Die1 without going through the I/O Die.

That could be more a curse than a blessing as you'd be creating an architecture that is non uniform again (NUMA) and be at the mercy of OS and application specific optimizations. One of the big goals of Zen2 is to remove the NUMA aspects as much as possible and confine that to the more traditional CPU socket zoning.

 

NUMA is not bad, in fact it can be extremely good, but it has to be done right and a large part of that doing it right is not on the shoulders of the CPU maker but on the software developers.

 

In lieu of being able to do full mesh a central I/O hub/die has the highest chance of compatibility and performance consistency. It can be beneficial to have a strong point but if it comes at the cost of having a weak point, when you are already considered inferior, it would be better to give up the strong point for all round good enough.

[Stefan Payne]

1 hour ago, leadeater said:

That could be more a cruse than a blessing as you'd be creating an architecture that is non uniform again (NUMA)

I really don't get that OS don't get it as the first x86 implementation of NUMA was over 15 years ago - Socket 940.

 

Quote

In lieu of being able to do full mesh a central I/O hub/die has the highest chance of compatibility and performance consistency. It can be beneficial to have a strong point but if it comes at the cost of having a weak point, when you are already considered inferior, it would be better to give up the strong point for all round good enough.

Yeah, I'd also say that the CPUs only have one IF Link and go to the I/O die and the Die to Die Communication is running through the I/O Die.

The advantage is that the CPU Die does not have to care or be designed for the amount of CPU Dies on the Package...

And it simplifies the design.

Edited January 27, 2019 by Stefan Payne
939 <-> 940 ARGH

[leadeater]

7 minutes ago, Stefan Payne said:

I really don't get that OS don't get it as the first x86 implementation of NUMA was over 15 years ago - Socket 939.

 

Operating systems can do it just fine, as I said NUMA for all of computing history has been across CPU sockets not within a CPU package. Also socket 939 was not the first, not by a long shot. Intel Pentium Pro from 1995 could do dual and quad socket, and I bet that wasn't the first either but the first I used anyway.

[Taf the Ghost]

5 hours ago, mr moose said:

-snip-

And a brand new, larger motherboard form factor to handle the power delivery. 

[mr moose]

Just now, Taf the Ghost said:

And a brand new, larger motherboard form factor to handle the power delivery. 

I would have thought anything with a 990fx chipset would have sufficed...  

[leadeater]

5 minutes ago, Taf the Ghost said:

And a brand new, larger motherboard form factor to handle the power delivery. 

I predict the coming 56 core SKU will have a dedicated secondary board for power delivery and a companion wave of dual motherboard cases 

[Taf the Ghost]

5 hours ago, mr moose said:

I would have thought anything with a 990fx chipset would have sufficed...  

I am a bit surprised that they're going to require 2 PSUs for the board. It really shouldn't draw that much power, but Intel has gone for hard overkill with the "HEDT" platform. I'm just not sure why.

 

5 hours ago, leadeater said:

I predict the coming 56 core SKU will have a dedicated secondary board for power delivery and a companion wave of dual motherboard cases 

https://ark.intel.com/products/120496/Intel-Xeon-Platinum-8180-Processor-38-5M-Cache-2-50-GHz-

 

At 4 Ghz, all-core, the CPU should be around 400w to the CPU. I really don't know why you'd need more than a 800w unit, unless Intel really is just attempting to break 3D Mark records for the next few years.

[mr moose]

3 minutes ago, Taf the Ghost said:

I am a bit surprised that they're going to require 2 PSUs for the board. It really shouldn't draw that much power, but Intel has gone for hard overkill with the "HEDT" platform. I'm just not sure why.

dual PSU's in the right case would look mad.  And we all know when it comes to CPU performance that feelings trump real world figures anyway.

[Stefan Payne]

Just now, leadeater said:

Also socket 939 was not the first, not by a long shot. Intel Pentium Pro from 1991 could do dual and quad socket, and I bet that wasn't the first either but the first I used anyway.

Ähm, 939 was Single Socket

940 was the Server one. And IIRC feature up 4 Sockets (or was it 8?)

 

But it was the first in the x86 implementation that features integrated memory controllers. As always, the RISC side of things was ahead of x86 in this area...

The stuff before that, again I'm only mentioning the x86 Market, had the Memory OCntroller in the CPU.

 

With NUMA in those, I assume that you're talking about multiple Chipsets/Systems "glued together"??

Didn't Compaq make some really awesome and interesting Stuff back in the early to late 90s in terms of Chipsets? (I remember the Compaq Triflex EISA Pentium Chipset with 128bit Memory Interface).

[Taf the Ghost]

5 hours ago, Stefan Payne said:

Ähm, 939 was Single Socket

940 was the Server one. And IIRC feature up 4 Sockets (or was it 8?)

 

But it was the first in the x86 implementation that features integrated memory controllers. As always, the RISC side of things was ahead of x86 in this area...

The stuff before that, again I'm only mentioning the x86 Market, had the Memory OCntroller in the CPU.

 

With NUMA in those, I assume that you're talking about multiple Chipsets/Systems "glued together"??

Didn't Compaq make some really awesome and interesting Stuff back in the early to late 90s in terms of Chipsets? (I remember the Compaq Triflex EISA Pentium Chipset with 128bit Memory Interface).

Before the consolidation of the late 90s, there were some funky system designs out there that no one remembers. 

 

5 hours ago, mr moose said:

dual PSU's in the right case would look mad.  And we all know when it comes to CPU performance that feelings trump real world figures anyway.

I honestly think the 28c system is really only coming out so de8aur & kingpin can go at it.

[Stefan Payne]

1 minute ago, Taf the Ghost said:

Before the consolidation of the late 90s, there were some funky system designs out there that no one remembers. 

Oh yeah, absolutely.

Who here remembers the NLX and LPX form factors. I do and I love it. And with what we have right now, I'd love to see a comback of the LPX Form factor - because that is what some people are trying to build X-D

 

And also bigger OEMs build their own Chipsets with some Special Features and stuff like that.

 

The Above mentioned Compaq for example, but there were also a ton of other Chipset manufacturers that nobody remembers...

[pas008]

3 minutes ago, Stefan Payne said:

Oh yeah, absolutely.

Who here remembers the NLX and LPX form factors. I do and I love it. And with what we have right now, I'd love to see a comback of the LPX Form factor - because that is what some people are trying to build X-D

 

And also bigger OEMs build their own Chipsets with some Special Features and stuff like that.

 

The Above mentioned Compaq for example, but there were also a ton of other Chipset manufacturers that nobody remembers...

actually miss chipset options, not like now

sometimes wish they would go back to allowing us to have that option but this soc type thing took off

[Taf the Ghost]

5 hours ago, Stefan Payne said:

Oh yeah, absolutely.

Who here remembers the NLX and LPX form factors. I do and I love it. And with what we have right now, I'd love to see a comback of the LPX Form factor - because that is what some people are trying to build X-D

 

And also bigger OEMs build their own Chipsets with some Special Features and stuff like that.

 

The Above mentioned Compaq for example, but there were also a ton of other Chipset manufacturers that nobody remembers...

I honestly don't miss the days of having to figure out the proper Northbridge + Southbridge combo to buy because there could be a 10% performance difference. 

 

5 hours ago, pas008 said:

actually miss chipset options,

sometimes wish they would go back to allowing us to have that option but this soc type thing took off

I don't miss needing 6+ PCI cards to do what is on the back of the motherboard now. SoCs have their purposes. 

[pas008]

1 minute ago, Taf the Ghost said:

I honestly don't miss the days of having to figure out the proper Northbridge + Southbridge combo to buy because there could be a 10% performance difference. 

I dont obviously from statement above

I liked having the option to pick and choose for the system

[Stefan Payne]

1 minute ago, pas008 said:

actually miss chipset options, not like now

sometimes wish they would go back to allowing us to have that option but this soc type thing took off

Yeah, absolutely.

But today, the CHipset is a "lame" I/O Bridge, especially on AMDs side its just a stupid PCIe x4 to S/ATA, USB and PCIe Switch.

There aren't any "real" Chipsets no more or the possibility for that.

1 minute ago, Taf the Ghost said:

I honestly don't miss the days of having to figure out the proper Northbridge + Southbridge combo to buy because there could be a 10% performance difference. 

Yeah, but that's something in the olden days like Socket A and before the memory Controller was integrated...

 

And especially on the Intel Side of Things it was awful, with LX, BX, EX and all the other garbage they did - like the i940GML (only supports 2GiB RAM and Single Core CPUs)...

[Taf the Ghost]

Just now, Stefan Payne said:

Yeah, absolutely.

But today, the CHipset is a "lame" I/O Bridge, especially on AMDs side its just a stupid PCIe x4 to S/ATA, USB and PCIe Switch.

There aren't any "real" Chipsets no more or the possibility for that.

Yeah, but that's something in the olden days like Socket A and before the memory Controller was integrated...

 

And especially on the Intel Side of Things it was awful, with LX, BX, EX and all the other garbage they did - like the i940GML (only supports 2GiB RAM and Single Core CPUs)...

Speaking of Intel, I really don't miss RAMBUS in consumer platforms.

[pas008]

23 minutes ago, Stefan Payne said:

Yeah, absolutely.

But today, the CHipset is a "lame" I/O Bridge, especially on AMDs side its just a stupid PCIe x4 to S/ATA, USB and PCIe Switch.

There aren't any "real" Chipsets no more or the possibility for that.

Yeah, but that's something in the olden days like Socket A and before the memory Controller was integrated...

 

And especially on the Intel Side of Things it was awful, with LX, BX, EX and all the other garbage they did - like the i940GML (only supports 2GiB RAM and Single Core CPUs)...

i'm hoping amds io chiplet will solve this though hate reading manuals for my needs

 

back then I could raid on a system or not,   choice

onboard or not, choice

raid or not, choice

I had the choice not stuffed with software shit

 

not sure if you got my drift but was like I was building for multiple things then not like now where it seems like i'm limited

 

back then I could simply pick chipset if I wanted 3 video cards a physx card and couple raid card

now I have to look at lanes shared with what and sometimes they dont state shit

 

and thx to 1x risers

 

[Taf the Ghost]

14 minutes ago, pas008 said:

i'm hoping amds io chiplet will solve this though hate reading manuals for my needs

 

back then I could raid on a system or not,   choice

onboard or not, choice

raid or not, choice

I had the choice not stuffed with software shit

 

not sure if you got my drift but was like I was building for multiple things then not like now where it seems like i'm limited

 

back then I could simply pick chipset if I wanted 3 video cards a physx card and couple raid card

now I have to look at lanes shared with what and sometimes they dont state shit

 

There was a period where Motherboards came with "good" but not "great" utility parts if you bought a little higher on the quality chart. Now, it's now a case of SoC functions that work at the minimal level or you have to pay for expensive add-ons. That mid-tier of quality kind of got lost in the movement, but we've seen responses like Intel Networking.

[leadeater]

48 minutes ago, Stefan Payne said:

Ähm, 939 was Single Socket

940 was the Server one. And IIRC feature up 4 Sockets (or was it 8?)

You're the one that said socket 939 was the first, it wasn't, neither did it support it but I just assumed you meant 940. Maybe you misunderstand what NUMA is?

[pas008]

14 minutes ago, Taf the Ghost said:

There was a period where Motherboards came with "good" but not "great" utility parts if you bought a little higher on the quality chart. Now, it's now a case of SoC functions that work at the minimal level or you have to pay for expensive add-ons. That mid-tier of quality kind of got lost in the movement, but we've seen responses like Intel Networking.

agreed,

intel started with their chipset mafia mindset first cutting out nvidia and via, think there was someone else too but my mind is blurry from whiskey

wish they kept to the option of another bridge longer hell even now, last 3 mobos  were ws plx models so I can have tv tuners hardware raids etc, i dont use them now as much but updating was kinda cock blocked in a way, forced to multituners, and limited bandwidth on pcie lanes, yes its faster but  it is becoming the death of multi cards,lucid  hydra 200 chip for example?

 

 

 

edit still think that lucid chip arc will make multi chips work better by splitting the work load

[leadeater]

50 minutes ago, Stefan Payne said:

But it was the first in the x86 implementation that features integrated memory controllers. As always, the RISC side of things was ahead of x86 in this area...

The stuff before that, again I'm only mentioning the x86 Market, had the Memory OCntroller in the CPU.

That isn't NUMA, integrated IMC is not a prerequisite to/for NUMA but having that and more than one socket/CPU does mean NUMA is now in the mix. You can still have NUMA and not have on die IMC.