AMD 12 core 24 thread Zen2 engineering sample benchmark leaked

[cj09beira]

1 hour ago, Taf the Ghost said:

I am a bit surprised that they're going to require 2 PSUs for the board. It really shouldn't draw that much power, but Intel has gone for hard overkill with the "HEDT" platform. I'm just not sure why.

probably so that people that will need 2 psus wont have to use those weird adapters

1 hour ago, Taf the Ghost said:

I honestly think the 28c system is really only coming out so de8aur & kingpin can go at it.

de8aur will probably play with it a little bit and then go back to his epyc server, if he is able to get some 64 core monsters on his hands, some records will be broken by a good margin. any amd marketing guy reading JUST DO IT!

[Taf the Ghost]

11 minutes ago, cj09beira said:

probably so that people that will need 2 psus wont have to use those weird adapters

de8aur will probably play with it a little bit and then go back to his epyc server, if he is able to get some 64 core monsters on his hands, some records will be broken by a good margin. any amd marketing guy reading JUST DO IT!

AMD's HEDT team has done pretty well at getting TR into the hands of a most of the "influencer" set. Been really cheap marketing for them, but I do agree with shipping the extreme OC'ers some Rome parts.

[Stefan Payne]

11 minutes ago, leadeater said:

You're the one that said socket 939 was the first,

ARGH, I'm getting old. Sorry.

I was thinking about that mainboard (or some other, similar to it), while writing it:

https://www.anandtech.com/show/1210/11

 

11 minutes ago, leadeater said:

it wasn't, neither did it support it but I just assumed you meant 940.

Yes, meant 940 and I was thinking about "normal" X86 Market, in the "High End Server Market", that is its own world. 

12 minutes ago, leadeater said:

That isn't NUMA, integrated IMC is not a prerequisite to/for NUMA but having that and more than one socket/CPU does mean NUMA is now in the mix. You can still have NUMA and not have on die IMC.

Yes but that was rather rare, wasn't it?
And more a thing for, what we call now, High Performance Computing area.

[GOTSpectrum]

12 minutes ago, cj09beira said:

probably so that people that will need 2 psus wont have to use those weird adapters

de8aur will probably play with it a little bit and then go back to his epyc server, if he is able to get some 64 core monsters on his hands, some records will be broken by a good margin. any amd marketing guy reading JUST DO IT!

AMD to de8aur 

Dont let your dreams (of 128 cores) be dreams 

[cj09beira]

that moment when cinebench scores best by using 2 different instances each with half the cores 

that moment when cinebench scores are given in cinebenches/s

[leadeater]

22 minutes ago, Stefan Payne said:

Yes but that was rather rare, wasn't it?
And more a thing for, what we call now, High Performance Computing area.

NUMA has traditionally only been a server thing, inter CCX communication is technically NUMA as well and so is between die on Threadripper and EPYC. The CCX and Threadripper stuff is extremely new to desktop computing, generally speaking desktop computing had no need for so was not NUMA aware but you also have to understand NUMA until now was always tied to multi socket systems so even when applications were NUMA aware they were on the proviso of that being multi socket.

 

Until Zen why would any software developer consider that there is non uniform memory access across/between cores on the CPU, such a thing simply did not exist. On the other hand for the most part developers shouldn't have to care about that anyway, specific cases that necessitate it exist, but the OS should correctly do thread management which Windows does not. That's not to say Windows hasn't been doing it well enough in the past though, someone tied Windows shoelaces together and EPYC/2990X made it take a too larger step and it fell on it's face.

[YourNewPalAlex]

Will zen 2 ryzen support DDR5 RAM?

[Trixanity]

45 minutes ago, YourNewPalAlex said:

Will zen 2 ryzen support DDR5 RAM?

No.

[porina]

7 hours ago, Taf the Ghost said:

I honestly think the 28c system is really only coming out so de8aur & kingpin can go at it.

Agreed, it has extreme overclocker written over it. It is a halo product, that probably only a handful of people would ever buy, as opposed to be given for promotional purposes. But that is its job. 

 

Anyone seriously needing more (Intel) cores would just go multi-socket. A monolithic design in one socket is a lot easier for software (or should that be programmers?) to get high performance out of. The problem is, as we're seeing now, is the price of scaling monolithic designs. Going modular will help in that, but it will take some time for software to catch up.

[Stefan Payne]

2 hours ago, YourNewPalAlex said:

Will zen 2 ryzen support DDR5 RAM?

1 hour ago, Trixanity said:

No.

Well, its not entirely correct as the Zen2 die doesn't support any memory, its the I/O Die.

So it is possible that future versions with a Zen2 Die might eventualy support DDR-5 SDRAM.

But they will be different and possibly incompatible to AM4 because of the new I/O Die they need.

 

So truth is: Zen2 CPU Die doesn't support anything other than IF.

 

[GoldenLag]

2 hours ago, YourNewPalAlex said:

Will zen 2 ryzen support DDR5 RAM?

unlikely. though it is possible. they havent exactly had too much a need in terms of bandwidth. 

 

AMD will likely move to DDR5 once AM4 expires in 2020 with motherboards and CPUs for DDR5 in 2021.

 

though that is pure speculation. Zen 2 can very much support DDR5 if they truly wanted to

[Stefan Payne]

36 minutes ago, GoldenLag said:

AMD will likely move to DDR5 once AM4 expires in 2020 with motherboards and CPUs for DDR5 in 2021.

I'd say that they do that as soon as possible, though they shouldn't be first and let Intel do the ironing out of the bugs...

 

 

ANyway:

 

@leadeater

It is possible that Matisse might have a different design and connects the Die to the other one.
And it might be that IF Clocks are decoupled from the Memory.

Is it proven that the Zen2 Dies have CCX?? Or is the "no CCX" (=8Core) approach still on the table?

 

 

Something else:

https://www.thestreet.com/investing/amd-cto-discusses-upcoming-products-14833554

 

Quote

Papermaster said AMD is mindful of the single-threaded performance gap that has remained for Ryzen, and promised his company will deliver "very exciting gains" in this area while maintaining its multi-threaded performance lead. "What you will see with our third-generation Ryzen really is simply outstanding gaming performance," he declared.

Interesting. Lets hope he is not wrong.

[Taf the Ghost]

@Stefan Payne , @leadeater

 

It's about 23 min into the video that Adored addressed some of the latency issues and provided some other information passed along to him. The high-res picture of the Zen2 Desktop package is the most interesting part. 

 

 

Direct link. AMD is going to run a Cross Design for all of the I/O needed on the Chiplet. However, the really important parts of the information is that beyond just it being a UMA design, it's going to be identical core to core latencies with IF speed detached from the Memory bus. Those two alone will help with gaming performance, along with solving a lot of the problems Windows has with the architecture. 

[Trixanity]

6 hours ago, Stefan Payne said:

Well, its not entirely correct as the Zen2 die doesn't support any memory, its the I/O Die.

So it is possible that future versions with a Zen2 Die might eventualy support DDR-5 SDRAM.

But they will be different and possibly incompatible to AM4 because of the new I/O Die they need.

 

So truth is: Zen2 CPU Die doesn't support anything other than IF.

 

Still a no.

 

Saying that it technically could, while true, would mean we'd have to consider a lot of things that are technically possible but wouldn't happen. It's a silly game.

[Stefan Payne]

4 hours ago, Taf the Ghost said:

It's about 23 min into the video that Adored addressed some of the latency issues and provided some other information passed along to him. The high-res picture of the Zen2 Desktop package is the most interesting part. 

Yeah, that is really interesting and could be changing some things. Really interesting.

 

Quote

Direct link. AMD is going to run a Cross Design for all of the I/O needed on the Chiplet. However, the really important parts of the information is that beyond just it being a UMA design, it's going to be identical core to core latencies with IF speed detached from the Memory bus. Those two alone will help with gaming performance, along with solving a lot of the problems Windows has with the architecture. 

yeah, we don't know the Frequency IF runs with. He mentioned that the IF Clock will not be the same as the Memory Clock.

So it might be possible that we see some higher clocks here. 

 

Question is:
How high the clock?

Or did they "just" implement a simple multiplier and IF runs with, for example, 2x Memory Clocks?

 

3 hours ago, Trixanity said:

Still a no.

 

Saying that it technically could, while true, would mean we'd have to consider a lot of things that are technically possible but wouldn't happen. It's a silly game.

No, its two different things.

Its like Asking in the Beginning if AMD Athlon or Intel Pentium 3 supports DDR-SDRAM.

 

We're kinda back in time, where the Memory Controller wasn't integrated in the CPU. 

[Taf the Ghost]

@Stefan Payne currently, IF runs at Memory clock, which is half of the listed DDR clocks. (2666 DDR4 is 1333 Memclock.) It made a lot of sense given that the interrelation of all of the clock domains within the CPU die.  However, with a chiplet setup, there doesn't seem a great reason to lock the two together. IF is going to be your Chiplet to Chiplet interconnect while the Memclock will be from the IMC to the Memory. There's already going to be a penalty to move from memory to IF, so this should look a lot more like the Intel Uncore system, in practice. Which means there's going to be a world of fun times for what you can clock the independent domains to.

 

We saw this play out when Skylake-X launched. At the time, it was slower in gaming than both Ryzen & K-SKU Kaby Lake parts because the Mesh added even more latency penalty than the IF-to-Memory transition did, along with higher core to core latency. Putting a hard OC on just the Mesh brought the performance in line, but that took a while for people to figure out. I suspect we're going to have a few BIOS iterations along those lines, as everyone figures out new ways of normalizing the performance with overclocking. That's been part of why, in a few scenarios, really high memory speeds on Ryzen first gen pays off so much, as you're actually dropping the latency within the IF domain.

[RobbinM]

Well said. In addition I like to think the ring bus is the most important thing that makes a CPU like the 9900K stand out from an inter-core latency and bandwith perspective. I thought they had scaled it to the max already on the 6-core chips but then the 8-cores happened. So far neither mesh or IF beat it, unfortunately. In my opinion the "successor" of ringbus failed. I wonder if we can see the future of inter-core communication if we take a look at GPU's because they boarded the parallelisation ship a lot sooner.

[Taf the Ghost]

1 hour ago, RobbinM said:

Well said. In addition I like to think the ring bus is the most important thing that makes a CPU like the 9900K stand out from an inter-core latency and bandwith perspective. I thought they had scaled it to the max already on the 6-core chips but then the 8-cores happened. So far neither mesh or IF beat it, unfortunately. In my opinion the "successor" of ringbus failed. I wonder if we can see the future of inter-core communication if we take a look at GPU's because they boarded the parallelisation ship a lot sooner.

They previously used dual rings for the big server chips, but the Ring Bus vs Mesh is probably even at 10 cores. Ring doesn't go beyond that but the Mesh does. For the scalable design approach that Intel takes, the Ring Bus is here to stay on Desktop for a long while.

[Trixanity]

10 hours ago, Stefan Payne said:

No, its two different things.

Its like Asking in the Beginning if AMD Athlon or Intel Pentium 3 supports DDR-SDRAM.

 

We're kinda back in time, where the Memory Controller wasn't integrated in the CPU. 

Doesn't really matter. It's all semantics. 

 

You're essentially arguing pigs can fly because you could transport them with a drone. And since a lot of things becoming true hinges on the notion that pigs can fly, we're in for a wild ride.

 

The question was quite straight forward but the meaning was essentially: will we see a consumer Zen 2 product with DDR5? The answer remains no.

 

Otherwise if someone asks "why won't they ditch HBM for Vega?" then you could say "hurr durr some Vega products already use DDR4 and there's even some that use GDDR5". You could say it but it doesn't really answer the question asked unless you interpret it at face value. You could add it as a side note or interesting tidbit but not as an answer on its own. 

 

Tl;dr 

[CarlBar]

AMD themselves have said it's impossible to go to DDR5 without a new socket.

[Stefan Payne]

Exctly, they need a new Socket and a New I/O Die, that is the minimum requirement.

That makes it NOT a Matisse based Chip.

 

BUT they still could use the same CPU Dies, that was my point...

[GoldenLag]

2 hours ago, Trixanity said:

will we see a consumer Zen 2 product with DDR5? The answer remains no.

actually the answer is closer to maybe. its unlikely, but they can if they want to

[Stefan Payne]

 

2 minutes ago, GoldenLag said:

actually the answer is closer to maybe. its unlikely, but they can if they want to

It depends when DDR5 is ready for Mass Market and how close Zen2+ or Zen3 is.

If DDR5 is ready, Zen2+ or 3 is not, there is no reason to wait for AMD, they are really flexible and can do whatever!

 

They don't have to touch the CPU part with that, they only need to revise the I/O Die (wich is mostly analogue/PHY stuff anyway)...

[GoldenLag]

6 minutes ago, Stefan Payne said:

 

It depends when DDR5 is ready for Mass Market and how close Zen2+ or Zen3 is.

If DDR5 is ready, Zen2+ or 3 is not, there is no reason to wait for AMD, they are really flexible and can do whatever!

 

They don't have to touch the CPU part with that, they only need to revise the I/O Die (wich is mostly analogue/PHY stuff anyway)...

its quite probable that we will see Consoles or similar systems using GDDR5 imo. simply because it cheaper and AMD will use Zen 2 as much as they can

[Stefan Payne]

20 minutes ago, GoldenLag said:

its quite probable that we will see Consoles or similar systems using GDDR5 imo. simply because it cheaper and AMD will use Zen 2 as much as they can

Naa, they are confirmed to use GDDR6.

But yeah, the speculation was that AMD will use the Zen2 CPU Die as much as they can, for selecting the CPUs the best they can.

 

Now that the Consoles *might* use the same CPU Chips, AMD might actually be able to do some heavy selection for some higher end, higher clocked Chips like "the other side" does. That is only possible because they have many CPUs to ship and can select the best of the best of the best for the Desktop Higher End Marked.