DDR5 is FINALLY HERE... and I've got it

[Emily Young]

You might think DDR5 is just another iteration on the same memory concept we've had since the beginning, but THIS is unlike any RAM you've ever used. Let's see what makes it tick, and how it can power the next generation of motherboards and CPUs.

 

 

[emosun]

I hope ddr5 ends up being more reliable than ddr4 , the number of threads here that are solved by removing ram is astounding 

[GodOfROG]

15 minutes ago, emosun said:

I hope ddr5 ends up being more reliable than ddr4 , the number of threads here that are solved by removing ram is astounding 

I love that its got ECC as part of the spec.

[emosun]

5 minutes ago, GodOfROG said:

I love that its got ECC as part of the spec.

I cant actually watch the video (on mobile) but I sure hope it just runs at the speed its runs at vs having to overclock it like ddr4. Life was real simple when ram just ran and worked.

[Nystemy]

Another big advantage with moving to a 32 bit bus is actually trace layout. Since these buses are independent, time skew between them don't matter. But all the 32 bits still need to be synched up with each other, that is however easier to do than 64 bits.

 

Another advantage of this easier trace layout is that it likely leads to marginally shorter traces, somewhat better signal integrity and potentially a fraction of a ns of less latency, but this last one is just an almost meaningless bonus. _{(The access latency of the whole memory system is still in the 10's of ns, removing a fraction of a ns doesn't really do much by this point.)}

 

Having some error correction as standard is though one of the biggest improvements to be fair. A lot of memory errors and blue screens after all comes from single bit errors. It is actually impressive how DRAM manufacturers can make chips with billions of DRAM cells without having a few drop like flies during the first few months. Or actually, a decent percentile of DRAM chip do fail just because of this. _{(Though, DRAM chips tends to have some "extra" magical space for the manufacturer to remap parts of the arrays into that were dead already in the factory (basic yield optimization), but this is practically only done at the factory, not on the fly where the product is out in the field.)}

 

Moving the power system to the module is a wise move to be fair. But I am surprised it takes its power from 5 volts and not 12. From the perspective of a DC-DC converter, it isn't a major difference. But maybe the DRAM manufacturers argued that working off 5 volts leads to marginally less noise and better performance for the same cost. Even if a few MLCC caps might have solved the issue, but DRAM is one of the most cost optimized components in a computer.

 

DDR5 makes some logical steps forward. But I personally still see it as a bit inept. _{(Been designing my own memory interface for a while (3-5 years) that is on paper better while using "off the shelf" technology that already exists on the market. But I am not a memory manufacturer, just some random furry that studies and develops computer architectures as a hobby.)}

[Levent]

The way Linus pronounces PMIC...

[Egg-Roll]

So... My computer has shotguns in it? Cool, tho I do prefer the deagle over the shotgun.

Luckily for me I shouldn't need to worry about adopters tax, assuming it doesn't linger longer than 2 years lol...

[porina]

32 minutes ago, emosun said:

I hope ddr5 ends up being more reliable than ddr4 , the number of threads here that are solved by removing ram is astounding 

Most (?) enthusiast systems use ram operating outside of standards, so is it really a surprise that you run into compatibility problems here and there? Not just speeds, also timing. If you have to enable XMP, that's the risk you're taking.

 

16 minutes ago, GodOfROG said:

I love that its got ECC as part of the spec.

Remember chip level is not same as module level ECC. I see this more as a cost optimisation measure for ram manufacturers than improving user reliability, with higher speeds and capacity increasing the chance a bad bit will ruin a chip. Cost of adding chip ECC is less than making perfect chips.

 

11 minutes ago, emosun said:

I cant actually watch the video (on mobile) but I sure hope it just runs at the speed its runs at vs having to overclock it like ddr4. Life was real simple when ram just ran and worked.

Doubt we'll go back to those days. As long as ram modules are produced outside standards you'll have the XMP thing. Get some JEDEC 3200 modules and they'll just work (on modern systems supporting that speed).

[Quackers101]

"nobody was harmed in PC's starting to shoot up the place with numbers".

 

just sad it's going to encourage other things, hopefully not messing with motherboards in price or layout.

then you got heat, and heatsinks, what pads, who is cheaping out? will there be thermal problems? the other components on the RAM like handling the voltage?

[Nystemy]

27 minutes ago, porina said:

Remember chip level is not same as module level ECC. I see this more as a cost optimisation measure for ram manufacturers than improving user reliability, with higher speeds and capacity increasing the chance a bad bit will ruin a chip. Cost of adding chip ECC is less than making perfect chips.

RAM manufacturers haven't made perfect chips in a very very long time.
Having a bit of extra array space and simply remapping the broken lines to working ones has been a thing since the 90's, likely even the 80's. This type of yield optimization is a very old school thing.

The in chip ECC part to what I have read is mainly there as to solve in flight errors when sending data to and from the CPU. Earlier generations had a simpler parity system in place to detect errors, but couldn't really solve them and were therefore forced to ask again, increasing bus utilization and latency.

Also, the "in chip ECC" to what I have read isn't actual error correction of the data in the array, but rather just error correction for the data being sent. So if a bit flip happens in the array, the data is now corrupt and the chip doesn't know. As stated above, this error correction is to be able to run at higher bus clock frequencies without minor errors being a problem. _{(This is one major part behind most error correction schemes in most systems. One can usually achieve higher overall bandwidth with error correction than without it.)}

 

So actual ECC memory modules will exist with the extra associated chip for fixing corruption in the arrays themselves, but this isn't what the in chip ECC is for.

Edit: After reading a bit from Micron's own documents.
The on die ECC is practically ECC. And DDR5 has CRC for the data in flight.
It is performed on every read request. Ensuring that the data is correct. There is also a scrub command that scans through the whole memory and fixes all errors. _{(I am surprised that this isn't done as part of array refreshing to be fair. But the industry is inept as usual.)}

 

If ECC modules will exist on the market or not is honestly a good question.

There is also soft (forgets with every reboot) and hard (nonvolatile) array remapping, so hopefully we will see a ton less broken memory modules in the future.

And as stated, there is error correction send along with the data as part of the bus. This is to ensure that any minor errors during flight can be fixed, instead of the CPU needing to ask for the data again. _{(since asking twice increases bus utilization and especially latency.)}

Edited October 26, 2021 by Nystemy

[whm1974]

So DDR5 is here but when are we going to modern CPU Sockets using it?  AMD AM5 and Inlet DDR5 Socket(x?) won't be released until when?

[Helpful Tech Witch]

2 minutes ago, whm1974 said:

So DDR5 is here but when are we going to modern CPU Sockets using it?  AMD AM5 and Inlet DDR5 Socket(x?) won't be released until when?

am5 next fall and alderlake with ddr5 on november 4th acording to leaks....

[whm1974]

1 minute ago, HelpfulTechWizard said:

am5 next fall and alderlake with ddr5 on november 4th acording to leaks....

according leaks... That is. Officially the Date is Unknown...

[Helpful Tech Witch]

Just now, whm1974 said:

according leaks... That is. Officially the Date is Unknown...

I mean its going to be soon anyways. People have been able to get 12900ks and we know its goign to be anounced at the inovation event tomorow

[porina]

21 minutes ago, Nystemy said:

If ECC modules will exist on the market or not is honestly a good question.

I'd imagine it will continue for those use cases where it is still needed.

 

21 minutes ago, Nystemy said:

And as stated, there is error correction send along with the data as part of the bus. This is to ensure that any minor errors during flight can be fixed, instead of the CPU needing to ask for the data again. _{(since asking twice increases bus utilization and especially latency.)}

I hadn't seen that claim for consumer grade DDR5 before. It was my understanding that on-chip ECC is meant to improve the integrity of the data held, but does not improve the risk to data corruption in transit.

 

14 minutes ago, whm1974 said:

according leaks... That is. Officially the Date is Unknown...

Intel have said Alder Lake will release this year, so that is a time window of now to end of year. Intel's event is being held over the next two days, where more details are expected to be released. So, we should have that date by the end of Thursday.

[Nystemy]

14 minutes ago, porina said:

I hadn't seen that claim for consumer grade DDR5 before. It was my understanding that on-chip ECC is meant to improve the integrity of the data held, but does not improve the risk to data corruption in transit.

Data corruption in transit is a different feature, I just threw it in together with the other stuff. Sorry for the confusion.

Also, DDR5 isn't even the first to have CRC for the data in flight. DDR4 had it for writes. _{(But didn't have it for reads for some odd reason.... I guess read latency is one reason, but the difference is a fraction of a ns, and as mentioned in a post far above, a fraction of a ns is almost pointless when talking to RAM.)}

[SolarNova]

If the MSRP and tier make up of GPU's, and feature set of CPUs*  of the last few generations is anything to go by, i highly suspect the DDR5 platforms to also be much more expensive, and also not have all the features of previous generations have had available.

 

E.G*

Quad channel

40+ lane PCi-E

HyperThreaded i7's

and so on.

 

 

It does certainly seem that as PC technology has become more and more mainstream, the benefit to consumers has diminished, whilst the profits of manufacturers has increased. I can only image the horrible state of affairs we'll be living with in another 10-15 years with GPU price tiers shifted another 2 or more tiers and CPU's with the bare minimum of feature sets being pushed as 'high end' options.

Its a shame manufactures are not being held to task over their actions, by the consumers or the media.

[whm1974]

1 hour ago, porina said:

I'd imagine it will continue for those use cases where it is still needed.

 

I hadn't seen that claim for consumer grade DDR5 before. It was my understanding that on-chip ECC is meant to improve the integrity of the data held, but does not improve the risk to data corruption in transit.

 

Intel have said Alder Lake will release this year, so that is a time window of now to end of year. Intel's event is being held over the next two days, where more details are expected to be released. So, we should have that date by the end of Thursday.

Is the HEDT CPU?

[Dutch_Master]

Anyone else noticed the flickering in the animated parts? For folks that are sensitive to that (think epilepsy) not a pleasant experience and potentially dangerous/deadly.

[poochyena]

2 hours ago, whm1974 said:

So DDR5 is here but when are we going to modern CPU Sockets using it?  AMD AM5 and Inlet DDR5 Socket(x?) won't be released until when?

Likely in the next 4 months. I believe both intel and amd confirmed their next gen CPUs will use DDR5

[ThomasBecker]

I love the background music. Can anyone identify the song name(s) for me? I tried it with track identifiers but somebody cant stop talking during the video ...

[Kilrah]

3 hours ago, emosun said:

I hope ddr5 ends up being more reliable than ddr4 , the number of threads here that are solved by removing ram is astounding 

Pretty much all of it is down to trying to push overclocking too far (i.e. marketing going "we don't have anything new to offer, we have to find a way to push sales another way") and dodgy memory controllers... My main PC was built with DDR4 right when it came out and it's been running perfectly fine for those 7 years at 2400...

[dogwitch]

6 minutes ago, Kilrah said:

Pretty much all of it is down to trying to push overclocking too far (i.e. marketing going "we don't have anything new to offer, we have to find a way to push sales another way) and dodgy memory controllers... My main PC was built with DDR4 right when it came out and it's been running perfectly fine for those 7 years at 2400...

where getting to the point with parts. that its already oc  from the factory. some times that makes the product not stable in the long run.

 

[porina]

2 hours ago, whm1974 said:

Is the HEDT CPU?

Alder Lake is a consumer level platform, not HEDT. Intel haven't said anything about new HEDT offerings as far as I'm aware.

[poochyena]

2 hours ago, ThomasBecker said:

I love the background music. Can anyone identify the song name(s) for me? I tried it with track identifiers but somebody cant stop talking during the video ...

Music is always credited in the description