DDR5 is FINALLY HERE... and I've got it

[GodOfROG]

2 hours ago, SolarNova said:

 

Its a shame manufactures are not being held to task over their actions, by the consumers or the media.

Waiting to see if AMD keeps it promise for Threadripper and keeping the socket. Then again Rumor is no consumer 5000 TR... but on one is talking about this either... yet.

[Quackers101]

2 hours ago, Dutch_Master said:

Anyone else noticed the flickering in the animated parts? For folks that are sensitive to that (think epilepsy) not a pleasant experience

agreed, some of those flashes was a bit too sharp and after each other. (quick flashes)

Was kind of painful, everything else wasn't that bad.

Not sure how it works for epilepsy.

[Dutch_Master]

19 minutes ago, Quackers101 said:

Not sure how it works for epilepsy.

Quickly flashing images can trigger an epilepsy attack for those sensitive to that. (I'm fortunate I do not belong in that demography!) Depending on the severity of such attack, it's potentially deadly. Some time ago there was a hype with (mainly) teens (of that era) to send such quickly flashing video files to people, preferably if they knew the recipient suffered from epilepsy. Regrettably, several people were quite badly injured as they watched the video and had an epileptic attack as a result. I can't recall fatalities, but statistically there should be as epilepsy at the time was not taken seriously by the general public. IIRC the hype changed that as it became clear this was a extremely severe form of bullying.

 

Mind, this was local (I'm not in the US, nor Canada) so it might have been different where you are.

[whm1974]

1 hour ago, porina said:

Alder Lake is a consumer level platform, not HEDT. Intel haven't said anything about new HEDT offerings as far as I'm aware.

Usually New Memory Tech is reserved for far more higher end and very expensive for Us Mortals.

[CommonTone]

Great video with some nice explanations, but please, as others have mentioned, please do not use such fast changing background textures (Timestamps 1:40, 3:33, 3:49, 4:57, 5:52 for nearly a minute in different ways, 8:48, etc). I don't even have epileptic sensitivity but it was extraordinarily distracting. Please do not do this.

[dogwitch]

1 hour ago, porina said:

Alder Lake is a consumer level platform, not HEDT. Intel haven't said anything about new HEDT offerings as far as I'm aware.

they really got nothing to compete with gen 2 or 3 TR.

now when linus said lower wattage ddr5....  multi tb of ram.... in a hedt platform..... in the future....

[minervx]

will ddr5 improve gaming performance?  will it take time for newer games to come out that fully utilize it?

[Gork]

Can someone give me a TLDR on DDR5? 

This isn't sounding like an improvement. 

Where is RAMs USB. In other words. Right now. If I get  Acme Ram 9000: DDR 4 lightspeed.  But then can oh say only get  Razer  Ram 9000  at light speed.  same  amount? well who knows. It'll work. that's un-fucking acceptable that shit needed to end decades ago. Give me a Ram type name. an amount a slot. and make it such that the computer doesn't give a fuck who made it. It'll just fucking work!

[Quackers101]

44 minutes ago, Dutch_Master said:

Quickly flashing images can trigger an epilepsy attack for those sensitive to that.

yeah, but I wonder if there is a scale for it and how can one identity the severity?

Flashing bright colors/scenes I get, but how much and when do one know when it will be bad? I guess if there was a program to delay/color correct with time to smooth out those kind of peak brightness/flashes? Some might just need more people to watch it, to know if people had an reaction to it? does certain mixes become more triggering of such an reaction? I just get the feeling it can be long but curious topic, not sure about the research for it.

[iamtechi27]

3 hours ago, poochyena said:

Music is always credited in the description

I only see the intro and outro music in the description. Am I blind?

[2plash6]

I wonder if the 12th gen Intel series and possibly Ryzen 5000 series will support it. Probably not though.

[Skipple]

This was an outstanding video. High level concepts explained in an easily digestible format. A+ to the team for this one.

[Kilrah]

7 hours ago, Gork said:

Where is RAMs USB. In other words. Right now. If I get  Acme Ram 9000: DDR 4 lightspeed.  But then can oh say only get  Razer  Ram 9000  at light speed.  same  amount? well who knows. It'll work. that's un-fucking acceptable that shit needed to end decades ago. Give me a Ram type name. an amount a slot. and make it such that the computer doesn't give a fuck who made it. It'll just fucking work!

It's always been that way as long as you run the standard clocks. 

It's only become a mess if trying to overclock, but as mentioned everybody's been trying to push to it. 

[dogwitch]

9 hours ago, minervx said:

will ddr5 improve gaming performance?  will it take time for newer games to come out that fully utilize it?

yes and no. 50% of games it wont matter. other half it it will.

jay2cent talk on this. but also how game dev for console affect pc version.. so

[porina]

10 hours ago, whm1974 said:

Usually New Memory Tech is reserved for far more higher end and very expensive for Us Mortals.

There may be some price premium, but you also get faster ram. How much would similar speed DDR4 cost? If you don't feel you will get a benefit from it, you're welcome to stick to the DDR4 platforms.

 

9 hours ago, dogwitch said:

they really got nothing to compete with gen 2 or 3 TR.

Intel HEDT has traditionally been derived from server offerings. Today, if someone needed an Intel based workstation they can still go Xeon. HEDT is in a weird position where it isn't exactly fully pro, but isn't exactly consumer level. On that basis I'd question if HEDT space even really needs to exist - that applies to AMD too. If Intel decides to return to that space, Sapphire Rapids seems like a logical point to do so, possibly towards the end of next year. Current Ice Lake doesn't seem worth doing.

 

7 hours ago, 2plash6 said:

I wonder if the 12th gen Intel series and possibly Ryzen 5000 series will support it. Probably not though.

We already know that 12th gen will support it. Intel is running an event today/tomorrow and more information about the product offering is expected, with sales rumoured to start next week.

 

On AMD side we're not likely to see it until we move beyond AM4 with the next generation (6000 series).

[Arika]

wonder if there is going to be motherboards that can support both DD4 and DD5 (like a few skylake board could do DDR3 and DDR4) so we can get an actual comparison to see what benefits DD5 can give using the exact same hardware.

[ThomasBecker]

14 hours ago, poochyena said:

Music is always credited in the description

No, sadly that is not the case. At least in this video. It is only mentioned the default intro and outro song.

[RejZoR]

2 hours ago, Arika S said:

wonder if there is going to be motherboards that can support both DD4 and DD5 (like a few skylake board could do DDR3 and DDR4) so we can get an actual comparison to see what benefits DD5 can give using the exact same hardware.

Question is if there even will be any, given there are also electrical changes. The memory VRM has been moved from motherboard to RAM. Which means you have an issue of raised cost because you'll have extra memory VRM circuitry for DDR4 that you don't need for DDR5. With DDR3 and DDR4 it was still on mobos, you just had 2 different physical slots for each. Another issue is way how DDR5 communicates with memory controller which might be fundamentally incompatible with new processors that might only support DDR5. Depending on model most likely.

 

Mobos with DDR3 and DDR4 were pretty rare and niche. I think DDR4 and DDR5 combo boards will be even more rare and even more expensive.

 

 

[WolframaticAlpha]

19 hours ago, porina said:

Remember chip level is not same as module level ECC. I see this more as a cost optimisation measure for ram manufacturers than improving user reliability, with higher speeds and capacity increasing the chance a bad bit will ruin a chip. Cost of adding chip ECC is less than making perfect chips

I wonder whether this means that ADL supports ECC ram.

[porina]

15 minutes ago, WolframaticAlpha said:

I wonder whether this means that ADL supports ECC ram.

Presuming you mean module ECC, historically I would have straight up said no, but Intel of today is not Intel of the past. I wouldn't count on it happening, but it isn't impossible either. We should know within 48 hours.

[whm1974]

4 hours ago, porina said:

There may be some price premium, but you also get faster ram. How much would similar speed DDR4 cost? If you don't feel you will get a benefit from it, you're welcome to stick to the DDR4 platforms.

 

Intel HEDT has traditionally been derived from server offerings. Today, if someone needed an Intel based workstation they can still go Xeon. HEDT is in a weird position where it isn't exactly fully pro, but isn't exactly consumer level. On that basis I'd question if HEDT space even really needs to exist - that applies to AMD too. If Intel decides to return to that space, Sapphire Rapids seems like a logical point to do so, possibly towards the end of next year. Current Ice Lake doesn't seem worth doing.

If I need to build another Rig atm, then I would be using DDR4 of course.

 

Intel left the HEDT Space? When did they do this and why? AMD still has the Threadripper, with even more Cores and Threads.

[porina]

1 minute ago, whm1974 said:

Intel left the HEDT Space? When did they do this and why? AMD still has the Threadripper, with even more Cores and Threads.

I don't know of any statement from them saying they left HEDT space, but it is obvious they have not released anything in that area since Cascade Lake. Quite simply they don't have anything worth offering. HEDT is a weird space. You have server like kit with consumer like configurations. Pro users could still go Xeon for workstations.

 

Intel may come back to that space, and if they do, I think the most logical point to do so is with Sapphire Rapids late next year.

[Nystemy]

15 hours ago, comander said:

pseudo-ECC. There isn't protection against data transmission errors.

DDR4 had CRC for data being sent to the memory, and DDR5 also introduces a CRC for reads as well.
So corruptions in transit will and can be fixed unless particularly severe.

But ECC were never implemented for mitigating in transit errors, but rather to combat errors accumulating over time in the array itself. Though, older ECC techniques implemented the actual correction in the memory controller, while DDR5 moves it into the individual memory chips instead, with the added feature of being able to scrub through the array and fix errors much faster than what the memory channel itself would be able to support.

[Nystemy]

3 minutes ago, comander said:

I'm just going to assume you know 10x what I do on the matter. It's on my to-do list to read and internalize this - https://semiengineering.com/what-designers-need-to-know-about-error-correction-code-ecc-in-ddr-memories/

The on die ECC is a logical step forward for the industry.

Since it brings forth the advantage that one don't have to correct both the corruption in the array on top of the corruption during transfer, but can rather fix each of these where they appear, making error correction easier since the two errors rarely will cancel out.

 

Another advantage is that the DDR5 ECC uses 8 bits for every 128 bits of data. (6.25% overhead)
Instead of 1 more DRAM chip for every 8 DRAM chips. (12.5% overhead)
And that makes the ECC feature a bit cheaper to implement on DDR5.

But then there is the issues of scaling down DRAM cells, the smaller they get, there worse they get. Meaning one gets errors more often.
And the smaller cells also tends to be harder to read to begin with. And this is actually a reason for dividing the memory into more banks, and bank groups. _{(Since the DRAM cell is effectively just a small capacitor holding a bit of charge in it, when the cell is read, that charged gets dumped onto the bit line, that slightly changes the voltage on the bit line is sensed by a set of comparators that in turn figure out if the bit line drifted or not. (This is why a row address change has a pre charge time to reset the bit lines to a known state before reading out the next set of cells.) After this read, the bit line is either put high or low depending on what were read, refreshing the row. (Really old DRAM didn't actually "auto refresh" on a read, but back then the DRAM cell capacitance were huge compared to the bit line itself, so the cell could drive the bit line a few times before needing to be refreshed. But DRAM makers quickly learned that a smaller cell means more cells per chip. And the "issue" of refreshing it isn't that hard to deal with.))} A smaller bank means shorter bit lines for the cells to drive. Though, more bank groups means more time for the sensitive measurement and one can then make the bit line longer again to have room for more cells.

 

But in the end.

I personally don't think DDR is all that perfectly made, but my own memory bus isn't even on the market, so what should I say...

[Siniko]

How will it handle the sync between the sub-lanes of the bus when the CPU request a 64bit data type? Because yeah, if I needed a 32bit integer type, and one of the sub-lanes is busy you can just use the other with DDR5, but the same applies otherwise; if I need a 64bit integer in the next burst, my request will be just waiting for the now busy sub-lane. This behavior could create some bottleneck issues when you have a process that uses randomly mixed data types with that length.