DDR5 is FINALLY HERE... and I've got it

[dogwitch]

8 hours ago, porina said:

I don't know of any statement from them saying they left HEDT space, but it is obvious they have not released anything in that area since Cascade Lake. Quite simply they don't have anything worth offering. HEDT is a weird space. You have server like kit with consumer like configurations. Pro users could still go Xeon for workstations.

 

Intel may come back to that space, and if they do, I think the most logical point to do so is with Sapphire Rapids late next year.

general this system are use for ml,vfx etc. lvl stuff.  i been watching a ton of people that do that content online and they all went to amd. people that where  brand loyal even left due to intel doing noting in that space.

 

[Gork]

6 hours ago, Nystemy said:

The on die ECC is a logical step forward for the industry.

Since it brings forth the advantage that one don't have to correct both the corruption in the array on top of the corruption during transfer, but can rather fix each of these where they appear, making error correction easier since the two errors rarely will cancel out.

 

Another advantage is that the DDR5 ECC uses 8 bits for every 128 bits of data. (6.25% overhead)
Instead of 1 more DRAM chip for every 8 DRAM chips. (12.5% overhead)
And that makes the ECC feature a bit cheaper to implement on DDR5.

But then there is the issues of scaling down DRAM cells, the smaller they get, there worse they get. Meaning one gets errors more often.
And the smaller cells also tends to be harder to read to begin with. And this is actually a reason for dividing the memory into more banks, and bank groups. _{(Since the DRAM cell is effectively just a small capacitor holding a bit of charge in it, when the cell is read, that charged gets dumped onto the bit line, that slightly changes the voltage on the bit line is sensed by a set of comparators that in turn figure out if the bit line drifted or not. (This is why a row address change has a pre charge time to reset the bit lines to a known state before reading out the next set of cells.) After this read, the bit line is either put high or low depending on what were read, refreshing the row. (Really old DRAM didn't actually "auto refresh" on a read, but back then the DRAM cell capacitance were huge compared to the bit line itself, so the cell could drive the bit line a few times before needing to be refreshed. But DRAM makers quickly learned that a smaller cell means more cells per chip. And the "issue" of refreshing it isn't that hard to deal with.))} A smaller bank means shorter bit lines for the cells to drive. Though, more bank groups means more time for the sensitive measurement and one can then make the bit line longer again to have room for more cells.

 

But in the end.

I personally don't think DDR is all that perfectly made, but my own memory bus isn't even on the market, so what should I say...

Bingo this is one of the (many) reasons. I'd crowing on about. While more memory is generally good. the more you end up needing to use at some point it won't work.  From what I can tell it's bassically because of a arms race: A lot of gamers wanting hollywood style games with about gajillion polygon is fucking hard AF on ram. Especially with syncronous technoloy. all we're doing is switching very quickly between parts of the MOBO, ram, etc.  Rather than being able to have on core of the CPU get the GPU ready to render lots of stuff and another set free up RAM to store some stuff. Which is possible in Asynchronous, or some highbred of the to. We'd still need memory. but probably not nearly as densely packed where  a lot of physics issues start to come up

 

Yet another, yet another issue is apps, are fucking awfully tooled. Garbage clean up? what's that! memory leaks,  keeping things reasonable? why bother! Games show these problems clear as day because of how much the ask of hardware.

[whm1974]

2 minutes ago, Gork said:

Bingo this is one of the (many) reasons. I'd crowing on about. While more memory is generally good. the more you end up needing to use at some point it won't work.  From what I can tell it's bassically because of a arms race: A lot of gamers wanting hollywood style games with about gajillion polygon is fucking hard AF on ram. Especially with syncronous technoloy. all we're doing is switching very quickly between parts of the MOBO, ram, etc.  Rather than being able to have on core of the CPU get the GPU ready to render lots of stuff and another set free up RAM to store some stuff. Which is possible in Asynchronous, or some highbred of the to. We'd still need memory. but probably not nearly as densely packed where  a lot of physics issues start to come up

 

Yet another, yet another issue is apps, are fucking awfully tooled. Garbage clean up? what's that! memory leaks,  keeping things reasonable? why bother! Games show these problems clear as day because of how much the ask of hardware.

dGPU Memory is of course a very different beast then Desktop RAM. The Former is very expensive per MB.The latter is way cheaper.

[Gork]

3 minutes ago, whm1974 said:

dGPU Memory is of course a very different beast then Desktop RAM. The Former is very expensive per MB.The latter is way cheaper.

^^^^

[porina]

10 hours ago, dogwitch said:

general this system are use for ml,vfx etc. lvl stuff.  i been watching a ton of people that do that content online and they all went to amd. people that where  brand loyal even left due to intel doing noting in that space.

Intel do offer Ice Lake workstation CPUs:

https://www.anandtech.com/show/16822/intel-launches-xeon-w-3300-3365-ice-lake-workstations-38-core

I guess this isn't visible to the consumer focus of most people on forums like here.

 

Intel still have Intel problems with that offering, in that they're notably more expensive if you compare core counts against Threadripper. Also Ice Lake is on Intel's older 10nm process which doesn't clock well, although that doesn't matter when multiple cores are active at once. After all, you don't usually buy high core count CPUs to rely on their single thread performance.

 

I keep mentioning Sapphire Rapids as a possible good point for Intel to re-enter the HEDT space. Expected in about a year (it's late too), it is expected to be based off the P cores in Alder Lake, probably with some differences in cache size and arrangement, although AMD might finally release Zen 3 Threadripper by then and it'll have a harder fight, and Zen 4 consumer will be nipping on its ankles.

[MultiGamerClub]

I'll wait to upgrade until AM5 or DDR5 becomes avaible.

[Nystemy]

22 hours ago, Siniko said:

How will it handle the sync between the sub-lanes of the bus when the CPU request a 64bit data type? Because yeah, if I needed a 32bit integer type, and one of the sub-lanes is busy you can just use the other with DDR5, but the same applies otherwise; if I need a 64bit integer in the next burst, my request will be just waiting for the now busy sub-lane. This behavior could create some bottleneck issues when you have a process that uses randomly mixed data types with that length. 

A 64 bit value wouldn't actually be distributed in that type of fashion.

 

To oversimplify things, the 32 bit wide bus is to a degree its own channel. Where data is simply multiplexed over it as needed. And the bus interface don't tend to work with individual variables but rather whole cache lines at once. One can partly think of DDR5 being two individual memory channels sharing a common address bus but having separate data buses while using a single connector. The memory controller will in general interleve the two "memory channels" across the address space, similar to how memory controllers interleve memory channels already.

 

Asking for a 64 bit value would only use the 32 bit bus leading to the memory chips that actually stores the data in question. The other 32 bits leads to the other chips that stores another portion of our address space within it isn't of interest.

[dogwitch]

14 hours ago, porina said:

Intel do offer Ice Lake workstation CPUs:

https://www.anandtech.com/show/16822/intel-launches-xeon-w-3300-3365-ice-lake-workstations-38-core

I guess this isn't visible to the consumer focus of most people on forums like here.

 

Intel still have Intel problems with that offering, in that they're notably more expensive if you compare core counts against Threadripper. Also Ice Lake is on Intel's older 10nm process which doesn't clock well, although that doesn't matter when multiple cores are active at once. After all, you don't usually buy high core count CPUs to rely on their single thread performance.

 

I keep mentioning Sapphire Rapids as a possible good point for Intel to re-enter the HEDT space. Expected in about a year (it's late too), it is expected to be based off the P cores in Alder Lake, probably with some differences in cache size and arrangement, although AMD might finally release Zen 3 Threadripper by then and it'll have a harder fight, and Zen 4 consumer will be nipping on its ankles.

true. but with intel pushing back said xeon for so long. it made user switch else where and cheaper. they lost many costumers on the server side.(still they have a lot) but when you drop the manf ball so hard. people start switching to other cpus.