AMD might announce their new CPU lineup on Tuesday

[GOTSpectrum]

17 minutes ago, leadeater said:

Wonder if we'll get a semi quick Zen2+ that has both DDR4 and DDR5 support or just DDR5 support. It's just so damn close to DDR5 it's a shame not to be able to use it right away. If we're really lucky Zen 2 actually does have support for both, with new motherboard required for DDR5 when they come available.

AMD has a long history of supporting multiple memory types on one chip... Am4+ anyone?

[descendency]

Now... if only AMD could do what they did for CPUs with Zen for GPUs...

[cj09beira]

3 hours ago, Taf the Ghost said:

The 7nm part with the cores should be what we're getting with Ryzen 3rd gen. It might, however, have significant chunks disabled in the Epyc 2 configuration. The one actual leak with any information about the +1 die's nature was that the platform will have some GenZ technology in it. I speculate that the +1 die is more like a Network Switch than an actual Central Hub that everyone is thinking about.

We don't know if the IMC is actually on the +1 die. AMD has a bunch of patents sitting out there about cache coherence and other details that point to there being interesting solutions for the potential problem. However, the place that matters most is on Desktop. 64 core server parts are going to care a lot more about memory bandwidth, but the +1 die could be doing some interesting things with establishing a shared memory space via the controller actually on the die.

so you think they might be passing IF through the memory controllers?, that doesn't seem too smart, i am confused right now hopefully we will know more on the 6th 

 

2 hours ago, leadeater said:

Wonder if we'll get a semi quick Zen2+ that has both DDR4 and DDR5 support or just DDR5 support. It's just so damn close to DDR5 it's a shame not to be able to use it right away. If we're really lucky Zen 2 actually does have support for both, with new motherboard required for DDR5 when they come available.

wasn't news a few months ago that amd had opened a ddr5 research lab, that would point to ddr5 still being quite some time away 

[Taf the Ghost]

7 hours ago, leadeater said:

Wonder if we'll get a semi quick Zen2+ that has both DDR4 and DDR5 support or just DDR5 support. It's just so damn close to DDR5 it's a shame not to be able to use it right away. If we're really lucky Zen 2 actually does have support for both, with new motherboard required for DDR5 when they come available.

I fully expect AM5 will be DDR5, which we could see in Late 2020.

[ravenshrike]

12 hours ago, Nicnac said:

it was a zen reveal last time but I believe this time Next Horizon is gonna be about Epyc chips only.

Could be an EPYC reveal and a basic Zen+ to Zen2 CCX performance comparison.

 

10 hours ago, GoldenLag said:

The question is if they want to spend money on a 14nm Die on Ryzen.

*shrugs* Pretty sure they still are obligated to produce something through GloFo, even if its no longer their primary processors.Could be an easy way to meet that fab's obligations.

[Taf the Ghost]

5 hours ago, cj09beira said:

so you think they might be passing IF through the memory controllers?, that doesn't seem too smart, i am confused right now hopefully we will know more on the 6th 

 

wasn't news a few months ago that amd had opened a ddr5 research lab, that would point to ddr5 still being quite some time away 

My thought is that the +1 die is more like a Switch that allows for some aspects to be Opaque to the rest of the system. I expect the chiplets to still be full SoCs, but the +1 die likely establishes some aspects of the clock domain and the Southbridge functions. Kind of like a massive PLX device for the system. (This is how GenZ will approach things in the future.)

 

7 hours ago, descendency said:

Now... if only AMD could do what they did for CPUs with Zen for GPUs...

The +1 for Epyc means it'll be coming to GPUs eventually. However, the uArch is going to need to be designed for it. The Navi cycle won't have a MCM part for Consumer (we're expecting it for Workstation/HPC though), but the post-Navi uArch should have something like that. It gets more important the lower the Node goes.

[leadeater]

1 hour ago, Taf the Ghost said:

[image]

Could you post the link to the full document of that?

[mr moose]

What, a reveal possibility in the tech world and WCCFtech haven't already written several articles both announcing and denouncing it?  They must be slipping.

[leadeater]

1 minute ago, mr moose said:

What, a reveal possibility in the tech world and WCCFtech haven't already written several articles both announcing and denouncing it?  They must be slipping.

I hate to use the term but... they only deal in fake news

[porina]

AMD are dropping a pretty big hint of "7" if you look at the Z. CPU or GPU though?

[leadeater]

2 minutes ago, porina said:

AMD are dropping a pretty big hint of "7" if you look at the Z. CPU or GPU though?

Better not be an R7 GPU, those were crap.

 

I don't think there will be much talk about GPUs though, it seems both too early and I hope they will just focus on one segment. AMD's just not good at juggling multiple things at once.

[porina]

2 minutes ago, leadeater said:

I don't think there will be much talk about GPUs though, it seems both too early and I hope they will just focus on one segment. AMD's just not good at juggling multiple things at once.

I've not kept up to date on rumours, if 7nm CPU or GPU was supposed to be next out. And on that 2nd part, now Intel's problem  

[leadeater]

7 minutes ago, porina said:

I've not kept up to date on rumours, if 7nm CPU or GPU was supposed to be next out. And on that 2nd part, now Intel's problem  

I'm not too sure about timing either, I just know Vega 7nm compute cards are coming soon and so is 7nm EPYC2. Which will actually come first, or both at same time don't know. Unless this event is going to have a large focus on EPYC2 I don't see much value in talking about 7nm Vega or 7nm Navi which is further away than both as far as I know.

[GoldenLag]

3 hours ago, ravenshrike said:

*shrugs* Pretty sure they still are obligated to produce something through GloFo, even if its no longer their primary processors.Could be an easy way to meet that fab's obligations.

Yeah, but glofo has other things than 14nm. Like 28nm and so fourth.

 

AMD might also use TSMC 16nm for ease of assembly. 

[Taf the Ghost]

2 hours ago, leadeater said:

Could you post the link to the full document of that?

I'm honestly not sure where I found it, I just noticed it in a folder the other day. But I can look.

[Taf the Ghost]

2 hours ago, leadeater said:

Could you post the link to the full document of that?

https://twitter.com/ogawa_tter/status/892508395147730944?lang=en

http://www.teratec.eu/library/pdf/forum/2017/Presentations/A7_02_Forum_TERATEC_2017_ DEMICHEL_ HPE.pdf

 

 

Some references to there being at least some Gen Z tech in Rome:

 

https://twitter.com/KOMACHI_ENSAKA/status/1034919187959840768

https://benchlife.info/amd-7nm-epyc-rome-now-start-sampling-with-tsmc-process-node-08302018/

 

[leadeater]

5 minutes ago, Taf the Ghost said:

http://www.teratec.eu/library/pdf/forum/2017/Presentations/A7_02_Forum_TERATEC_2017_ DEMICHEL_ HPE.pdf

Thanks, think I remember reading this before or at least another one with most of the same slides in it. It's really hard to know what is and isn't public information 

[Taf the Ghost]

@leadeater

 

 

Page 7. Note the 2019 expectation from 64 cores being available. This is a 2017 presentation.

[Taf the Ghost]

13 minutes ago, leadeater said:

Thanks, think I remember reading this before or at least another one with most of the same slides in it. It's really hard to know what is and isn't public information 

On page 9, it seems to imply that Rome will be 12 channel.

[GoldenLag]

1 minute ago, Taf the Ghost said:

On page 9, it seems to imply that Rome will be 12 channel.

Wouldnt it make more sence to be 16 channel based on CCX count?

[Taf the Ghost]

3 minutes ago, GoldenLag said:

Wouldnt it make more sence to be 16 channel based on CCX count?

Probably, but can they fit that in a 2U system? And if we've got significant GenZ design within it, the DDR4 controllers might operate a bit differently. 

[GoldenLag]

9 minutes ago, Taf the Ghost said:

Probably, but can they fit that in a 2U system? And if we've got significant GenZ design within it, the DDR4 controllers might operate a bit differently. 

Possible HBM solutions maybe?

 

The only issue i see is how they are going to give the CPU cores bandwidth.  

[Taf the Ghost]

32 minutes ago, leadeater said:

Thanks, think I remember reading this before or at least another one with most of the same slides in it. It's really hard to know what is and isn't public information 

Looking at the design layouts, I think page 18 is all we're getting, of Gen Z, on Rome. It's going to have the Gen Z switch in place, but that's likely on the +1 die. This will radically open up AMD's Semi-Customs group in the CPU space. However, it also means there's some interesting things going on within the CPU domain itself.

 

@GoldenLag

 

Thinking about it, a 12 channel setup would let AMD have one failed channel per 2 die pair. My thinking is they're still going to be running the 4 "die" system from Epyc 1, but there will be 2 dies in a pair that has a memory domain common to each other. The IF system already can do some pretty significant load balancing with all channels onto a single Core. We'll see, obviously, but from where their design currently is at, it makes sense in an evolutionary fashion.

[Taf the Ghost]

5 minutes ago, GoldenLag said:

Possible HBM solutions maybe?

 

The only issue i see is how they are going to give the CPU cores bandwidth.  

The GenZ switch would allow for local memory as an add-on, but on-die memory seems like a few generations off still. Not the least of which is high cost issues still. 

[leadeater]

33 minutes ago, Taf the Ghost said:

Looking at the design layouts, I think page 18 is all we're getting, of Gen Z, on Rome.

Well we can only use what ever products actually have Gen-Z and the easiest right now is SCM, Gen-Z NVMe would be the next easiest. Those are just the same products with updated Gen-Z controllers in front of the DRAM/NAND etc. I do expect to see in chassis SCM though (Page 20).

Edited November 5, 2018 by leadeater