AMD might announce their new CPU lineup on Tuesday

[Guest]

4 minutes ago, MandoPanda said:

Serious missed opportunity here.

I think their lineup is pretty full they have so Zeny processors.

[MandoPanda]

1 hour ago, RorzNZ said:

I think their lineup is pretty full they have so Zeny processors.

[leadeater]

1 hour ago, RorzNZ said:

I think their lineup is pretty full they have so Zeny processors.

@Drak3 You'll like this joke, great NZ humor 

[Dylanc1500]

So how long until Intel pulls something similar to the stacked pentium 4, or an updated Teraflops Research Chip? The never really said much more on them afterwards. I know they have still been researching those concepts but haven't heard much. I'd like to see a 9900k with the LLC directly under the core and then shove to cores closer together decreasing intra-core latencies.

 

Who knows maybe IBM can license the Silicon Photonics from Intel and actually get somewhere with it. I want 1-2 ns memory and I/O devices latencies.

[Taf the Ghost]

1 minute ago, Dylanc1500 said:

So how long until Intel pulls something similar to the stacked pentium 4, or an updated Teraflops Research Chip? The never really said much more on them afterwards. I know they have still been researching those concepts but haven't heard much. Who knows maybe IBM can license the Silicon Photonics from Intel and actually get somewhere with it. I want 1-2 ns memory and I/O devices latencies.

They'll pull something, but their problem is their Node. AMD is now on TSMC, which is pretty much funded by Apple in the first place, at this point. They'll eventually get something called 10nm out, but they'll probably be in a hurry to move to their own 7nm node. They've got more than enough cash to weather this issue.

[Dylanc1500]

22 minutes ago, Taf the Ghost said:

They'll pull something, but their problem is their Node. AMD is now on TSMC, which is pretty much funded by Apple in the first place, at this point. They'll eventually get something called 10nm out, but they'll probably be in a hurry to move to their own 7nm node. They've got more than enough cash to weather this issue.

Thing is, everyone is at a point where they are running out of space. By that I mean llc and core to core traces (due to such high core counts with these large cores) distances are creating large amounts of latency. Even TSMC's node doesn't help. A slight redesign by putting the LLC and ring directly underneath the cores, and shoving all cores closer together would decrease latency and increase throughput massively. It could help with x, y package size as well. AMD could use the same concept and it would help them insanely.

 

heck I don't care if AMD does it. I just don't want to deal with POWER5 again... 

 

No, I FORBID it lol.

[leadeater]

5 minutes ago, Dylanc1500 said:

Thing is, everyone is at a point where they are running out of space. By that I mean llc and core to core traces (due to such high core counts with these large cores) distances are creating large amounts of latency. Even TSMC's node doesn't help. A slight redesign by putting the LLC and ring directly underneath the cores, and shoving all cores closer together would decrease latency and increase throughput massively. It could help with x, y package size as well. AMD could use the same concept and it would help them insanely.

I think AMD was looking at something similar with that concept CPU/GPU/HBM package where they were stacking. Maybe someone can quickly find that news story so I can refresh my memory on it.

[porina]

I had also wondered if more could be made of the vertical direction, but a concern would be power density. Doing more in the same area... could be challenging.

[Dylanc1500]

4 hours ago, leadeater said:

I think AMD was looking at something similar with that concept CPU/GPU/HBM package where they were stacking. Maybe someone can quickly find that news story so I can refresh my memory on it.

 

46 minutes ago, porina said:

I had also wondered if more could be made of the vertical direction, but a concern would be power density. Doing more in the same area... could be challenging.

I couldn't find anything from AMD in regards to CPU but I did find a bunch in regards to stacking memory (HBM).

 

Here is a study done by Intel with a pentium 4 and a core 2 duo. It gives a great explaination of doing a die to die stacking. Since the cache produces neglible heat stacking doesn't effect peak thermals too much. It's actually a very interesting read.

 

http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.130.6198&rep=rep1&type=pdf

[The Benjamins]

7 hours ago, Dylanc1500 said:

So how long until Intel pulls something similar to the stacked pentium 4, or an updated Teraflops Research Chip? The never really said much more on them afterwards. I know they have still been researching those concepts but haven't heard much. I'd like to see a 9900k with the LLC directly under the core and then shove to cores closer together decreasing intra-core latencies.

 

Who knows maybe IBM can license the Silicon Photonics from Intel and actually get somewhere with it. I want 1-2 ns memory and I/O devices latencies.

Well Intel did announce the 48c 2 die CPU 2 days before AMD. That thing is going to be not much faster then 2 of the 8180m. It is going to need a new socket with around 6000 pins, and has a TDP of 350w.

The only advantage I see is that it has 12 Channels of ram.

 

https://www.anandtech.com/show/13535/intel-goes-for-48cores-cascade-ap

[Dylanc1500]

4 hours ago, The Benjamins said:

Well Intel did announce the 48c 2 die CPU 2 days before AMD. That thing is going to be not much faster then 2 of the 8180m. It is going to need a new socket with around 6000 pins, and has a TDP of 350w.

The only advantage I see is that it has 12 Channels of ram.

 

https://www.anandtech.com/show/13535/intel-goes-for-48cores-cascade-ap

Yes I know, but that still comes back to my initial complaint of size restrictions of die and latency issues.

[The Benjamins]

1 minute ago, Dylanc1500 said:

Yes I know, but that still comes back to my initial complaint of size restrictions of die and latency issues.

I don't see intel getting anything better until 10nm hits

[Dylanc1500]

47 minutes ago, The Benjamins said:

I don't see intel getting anything better until 10nm hits

No, but that's why I mentioned bringing forth die stacking that they have displayed a couple times previously. As it allows them to use the same node and shrink the amount of x, y space they take up. They wouldn't need a better node, but (and this goes for AMD as well) once they did it would just allow for more improvement as it would compound the effects of smaller nodes.

 

12 hours ago, Dylanc1500 said:

Thing is, everyone is at a point where they are running out of space. By that I mean llc and core to core traces (due to such high core counts with these large cores) distances are creating large amounts of latency. Even TSMC's node doesn't help. A slight redesign by putting the LLC and ring directly underneath the cores, and shoving all cores closer together would decrease latency and increase throughput massively. It could help with x, y package size as well. AMD could use the same concept and it would help them insanely.