AMD might announce their new CPU lineup on Tuesday

[Mira Yurizaki]

3 minutes ago, PacketMan said:

Only if you listen to the marketing guys

Then again node size since like 32nm hasn't even described anything meaningful anymore

[leadeater]

2 hours ago, M.Yurizaki said:

So is it really a 7nm processor if it still has 14nm components?

Maybe that's to keep socket/motherboard compatibility?

[Tech_Dreamer]

is it okay to get disappointed much earlier before the release & ease off the damage i usually get from expecting too much from AMD?

[Coaxialgamer]

So where is this livestream?  If it ended , has AMD posted it yet?

[cj09beira]

1 minute ago, Coaxialgamer said:

So where is this livestream?  If it ended , has AMD posted it yet?

last 3 videos https://www.youtube.com/channel/UCF3xvZsD5e1IWNkLlEMyx9g/videos

[Taf the Ghost]

https://www.reddit.com/r/Amd/comments/9uscqu/epyc_and_epyc_2_dies_compared/

 

Quote

I'm no Photoshop expert, so this probably isn't the best.

But, here are the die sizes I estimate from this comparison (W x H):
Single Chiplet ~ 7.5mm x 9mm (67.5mm² )
Uncore/IO ~ 15.5mm x 25mm (387.5mm² )
Summit Ridge ~ 22.06mm x 9.66mm (213mm² )

Chiplets around 70mm² and the I/O die around 390mm². Which is pretty close to half way between Polaris and Vega in die size. (244 for Polaris and 510 for Vega.) Yields should be good, and smaller variants will yield even better.

[Mira Yurizaki]

12 minutes ago, leadeater said:

Maybe that's to keep socket/motherboard compatibility?

That shouldn't matter. I think compatibility is more of a firmware thing assuming all the communication lines are fine

[mr moose]

1 hour ago, BlueThumb said:

https://www.tomshardware.com/news/amd-new-horizon-7nm-cpu,38029.html

 

AMD Announces 64-Core 7nm Rome CPUs, 7nm MI60 GPUs, And Zen 4. 

"If AMD can field 7nm processors early this year, it will mark the first time in the company's history that it has had a process node leadership position over Intel. That should equate to faster, denser, and less power-hungry processors than Intel's 14nm chips."

 

I guess I should have bought AMD when it was down around $17 per share only a a couple weeks back. 

Depends on who you talk to, some people will argue that Intel already has 10nm out in some products which is equivalent to AMD 7nm.  Of course I would argue that doesn't mean much outside of technicalities because whats important to me is what I can buy and how much it costs. 

[leadeater]

3 minutes ago, M.Yurizaki said:

That shouldn't matter. I think compatibility is more of a firmware thing assuming all the communication lines are fine

It shouldn't, at least not for EPYC that is a SoC and no real chipset connectivity like other designs but you never know. I also know in electronics signals transmissions smaller node sizes are actually not as good because they can't handle as much power or heat, maybe something like that is in play for PCIe?

[Taf the Ghost]

@leadeater

 

Thinking about a Threadripper 3, it strikes me as PCIe 4.0 boards with 6-channel memory seems prudent. It'll allow them to use defective I/O dies, up to 48 cores for the platform and just utterly slaughter Intel out of the HEDT space.

 

I also think we're going into the era of AMx(+) again, which would explain some of the statements AMD has made. The 2020 Raven Ridge will be drop-in supported, but Zen 3 won't arrive until 2021 on Desktop. I don't foresee AMD just giving up bringing PCIe 4.0 to Desktop, so they'd need another Chipset/Board set for it. That would be AM4+ and the high-end boards.

 

On that 2-die Domain I mentioned. The 8c chiplets put back to back will be physically closer than the previous CCXs were to each other. The system is going to treat 2 dies as a single unit of 4 x 4 CCX.

[Taf the Ghost]

2 minutes ago, mr moose said:

Depends on who you talk to, some people will argue that Intel already has 10nm out in some products which is equivalent to AMD 7nm.  Of course I would argue that doesn't mean much outside of technicalities because whats important to me is what I can buy and how much it costs. 

The busted 10nm silicon does exist. Somewhere in the ether.

[cj09beira]

3 minutes ago, Taf the Ghost said:

@leadeater

 

Thinking about a Threadripper 3, it strikes me as PCIe 4.0 boards with 6-channel memory seems prudent. It'll allow them to use defective I/O dies, up to 48 cores for the platform and just utterly slaughter Intel out of the HEDT space.

 

I also think we're going into the era of AMx(+) again, which would explain some of the statements AMD has made. The 2020 Raven Ridge will be drop-in supported, but Zen 3 won't arrive until 2021 on Desktop. I don't foresee AMD just giving up bringing PCIe 4.0 to Desktop, so they'd need another Chipset/Board set for it. That would be AM4+ and the high-end boards.

 

On that 2-die Domain I mentioned. The 8c chiplets put back to back will be physically closer than the previous CCXs were to each other. The system is going to treat 2 dies as a single unit of 4 x 4 CCX.

btw amd didn't confirm the number of cores per ccx, did they?

[Mihle]

Why is the IO chip so big?

[mr moose]

3 minutes ago, Taf the Ghost said:

The busted 10nm silicon does exist. Somewhere in the ether.

Just a handful of niche products here and there.  Certainly not  a major production though.

[Taf the Ghost]

Just now, mr moose said:

Just a handful of niche products here and there.  Certainly not  a major production though.

The fact they can't yield a working GPU is the weird part. Or it explains why they've had to spend so much time fixing problems.

[leadeater]

6 minutes ago, cj09beira said:

btw amd didn't confirmed the number of cores per ccx, did they?

Should be 8 per CCX, just going by math. 64 cores / 8 chiplets (CCXs). Though each chiplet could also be 2 CCXs.

 

Also for those that haven't seen this, disclaimer these are rumors.

 

 

 

Quad socket support??!??!

[Taf the Ghost]

3 minutes ago, cj09beira said:

btw amd didn't confirm the number of cores per ccx, did they?

I haven't seen any confirmation. We just know the chiplets are 8 cores. They could be in an 8 core Ring with that large L3 cache, but we'll find out soon enough.

 

I'm expecting the chiplet to be center-line symmetrical, though.

[Mira Yurizaki]

4 minutes ago, leadeater said:

It shouldn't, at least not for EPYC that is a SoC and no real chipset connectivity like other designs but you never know. I also know in electronics signals transmissions smaller node sizes are actually not as good because they can't handle as much power or heat, maybe something like that is in play for PCIe?

The chip itself could be smaller, just feeding signals into some other component that provides what the rest of the system wants.

 

I'm still going with this being an engineering decision to make this part on a larger node because what it does wouldn't benefit from going smaller for the cost it would need. And you don't have to be worrying about manufacturing yet another part on a new process node

[mr moose]

Just now, Taf the Ghost said:

The fact they can't yield a working GPU is the weird part. Or it explains why they've had to spend so much time fixing problems.

I reckon they just aimed too high with the whole thing.   Had they pulled it off as planned it might have been mammoth, but now it's just meh and frankly the whole 10nm thing from intel feels like the whole GCN thing from AMD, a long time to improve and develop and not much to show for it when it gets here.

[Taf the Ghost]

1 minute ago, mr moose said:

I reckon they just aimed too high with the whole thing.   Had they pulled it off as planned it might have been mammoth, but now it's just meh and frankly the whole 10nm thing from intel feels like the whole GCN thing from AMD, a long time to improve and develop and not much to show for it when it gets here.

Apparently Icelake is a pretty good improvement over Skylake, but it also taped out in H2 2017 and it might not see Desktop until H1 2020. Rough times for their Engineers.

[S w a t s o n]

1 hour ago, Taf the Ghost said:

I haven't seen any confirmation. We just know the chiplets are 8 cores. They could be in an 8 core Ring with that large L3 cache, but we'll find out soon enough.

 

I'm expecting the chiplet to be center-line symmetrical, though.

We were both sort of right lul. I will give credit that we dont know if it's a 8 core single ccx die or just real small 2ccx zepplin dies, but I'll take 8core chiplet

[mexican-bum]

1 hour ago, Mihle said:

Why is the IO chip so big?

It is still 14 nm

[Mihle]

21 minutes ago, mexican-bum said:

It is still 14 nm

I know but it's bigger than what a Zen 1 chip was and it doesn't even have any cores in it.

[S w a t s o n]

1 hour ago, Mihle said:

I know but it's bigger than what a Zen 1 chip was and it doesn't even have any cores in it.

It has the IO portion for all 8 chiplets, this is IO and Infinity Fabric, it's also 14nm so the transistors are basically twice as large which does impact final size a fair bit. If each chiplet is a single 8 core CCX that could further complicate things as each 4 core CCX in the zen 1 zepplin dies had their own interconnect circuitry too besides the infinty fabric to the other dies. So it may have to house that stuff too

 

It may or may not contain cache and other things as well.

[leadeater]

2 hours ago, S w a t s o n said:

It may or may not contain cache and other things as well.

They'll have L1 and L2 cache at a minimum, I'm very interested to know how the L3 cache is done and if there is any extra in the I/O die/L4 cache or something.

 

Edit:

Hmm might have read that wrong, you were meaning cache in the I/O module?