AMD might announce their new CPU lineup on Tuesday

[S w a t s o n]

21 minutes ago, leadeater said:

They'll have L1 and L2 cache at a minimum, I'm very interested to know how the L3 cache is done and if there is any extra in the I/O die/L4 cache or something.

There's no way L1 and L2 are moving off of silicon that is physically connected to the cores

[S w a t s o n]

23 minutes ago, leadeater said:

They'll have L1 and L2 cache at a minimum, I'm very interested to know how the L3 cache is done and if there is any extra in the I/O die/L4 cache or something.

 

1 minute ago, S w a t s o n said:

There's no way L1 and L2 are moving off of silicon that is physically connected to the cores

The retired engineer's drawings you posted seem to agree. L1 and L2 needs to be lightspeed

https://pbs.twimg.com/media/DrOjne3U0AAyWZr.jpg

 

 

[Mira Yurizaki]

6 hours ago, leadeater said:

Should be 8 per CCX, just going by math. 64 cores / 8 chiplets (CCXs). Though each chiplet could also be 2 CCXs.

 

Also for those that haven't seen this, disclaimer these are rumors.

 

Quad socket support??!??!

I feel like this is going to take a metric butt-ton of high performance RAM to keep it from getting starved.

[leadeater]

2 hours ago, S w a t s o n said:

There's no way L1 and L2 are moving off of silicon that is physically connected to the cores

Yea I was meaning the chiplets (CCXs) would have L1 and L2 cache min. Got mixed up because the second part you were talking about the CCXs but the main thing was about the I/O die. Hence my edit.

[leadeater]

1 hour ago, M.Yurizaki said:

I feel like this is going to take a metric butt-ton of high performance RAM to keep it from getting starved.

Yep, though with good optimization you can get a ton more performance by making sure operations are in optimal sizes for the data caches meaning you won't thrash the system memory as much. You can get up to 10x AVX performance even on Intel platforms when doing that.

 

Not sold on that 8 channel memory being correct though, double the number of cores with no more memory lanes. That's putting a ton of faith in the restructure of the CCXs being good enough.

[Taf the Ghost]

3 hours ago, M.Yurizaki said:

I feel like this is going to take a metric butt-ton of high performance RAM to keep it from getting starved.

The assumption, from some of the presentations we've seen, would be that it'll handle 3200 at the Server level, though that's really a prelude to DDR5. Thus, it makes sense.

1 hour ago, leadeater said:

Yea I was meaning the chiplets (CCXs) would have L1 and L2 cache min. Got mixed up because the second part you were talking about the CCXs but the main thing was about the I/O die. Hence my edit.

The L3 will be on the chiplets, but we're not sure exactly how they're going to be aligned. We should find out in AMD gives their Consumer event in January.

[leadeater]

9 hours ago, Taf the Ghost said:

I haven't seen any confirmation. We just know the chiplets are 8 cores. They could be in an 8 core Ring with that large L3 cache, but we'll find out soon enough.

 

I'm expecting the chiplet to be center-line symmetrical, though.

Well some good actual information, those rumor diagrams have a lot wrong. The chiplets have the PCIe lanes, makes sense because AMD likes to directly connect dies/chiplets across sockets for minimal hop count.

 

https://www.youtube.com/watch?v=YmPimQp7xLE

[Dylanc1500]

I'm really beginning to feel like AMD is starting to follow IBM's POWER direction with some of the decisions they are making. They are eerily similar to POWER7 but with "x86" and only two-way SMT. Heck they even run about the same clock speed.

 

Edit: by the way here is a sneak peak for Zen 3 EPYC

 

 

Not serious.

[leadeater]

@Taf the Ghost

The FMA units have been increased from 128bit to 256bit, oh yea full AVX2 throughput (relative to Intel).

[Taf the Ghost]

Just now, leadeater said:

@Taf the Ghost

The FMA units have been increased from 128bit to 256bit, oh yea full AVX2 throughput (relative to Intel).

Yup. Saw some discussion, and it appears they just changed the 128bit units to 256bit units. I guess that makes design easier, though the Front End changes probably matter more than anything else. Main thing is Threadripper 3 is going to murder Intel's HEDT offerings.

 

Zen 3 is going to be out relatively quick compared to Zen 2 because it looks like just an iteration on the current design. Thinking about it yesterday, I don't think Milan will have DDR5, unless they've found a way to have the IMC handle both DDR4 & 5 in the same unit. I wonder if that points to issues with DDR5 in the industry?

 

The drop-in compatibility is clever move. Seems strange in Server, but with AMD's market position, this will allow all of those Server System Designs to be reused until ~2022. They'll add in PCIe 4.0 designs as well, but, as of yet, very little is coming to PCIe 4.0 that quickly. It isn't any faster, just more total bandwidth.

[Taf the Ghost]

@Dylanc1500

 

 

Someone on Reddit adjusted them enough for measurements, but it's interesting that this was clearly AMD's plan when they laid out their chiplet strategy. Though part of me really does like the 45 degree angle designs. Always just something cool about them.

[GoldenLag]

Just now, Taf the Ghost said:

Someone on Reddit adjusted them enough for measurements, but it's interesting that this was clearly AMD's plan when they laid out their chiplet strategy. Though part of me really does like the 45 degree angle designs. Always just something cool about them.

i am assuming they put 2 chips close together for easy soldering process

[leadeater]

2 minutes ago, Taf the Ghost said:

Yup. Saw some discussion, and it appears they just changed the 128bit units to 256bit units. I guess that makes design easier, though the Front End changes probably matter more than anything else.

Increasing the width of the FMAs was what I was expecting, easiest thing to do.

 

3 minutes ago, Taf the Ghost said:

Zen 3 is going to be out relatively quick compared to Zen 2 because it looks like just an iteration on the current design. Thinking about it yesterday, I don't think Milan will have DDR5, unless they've found a way to have the IMC handle both DDR4 & 5 in the same unit. I wonder if that points to issues with DDR5 in the industry?

Strictly EPYC2 for now, unless Ryzen goes chiplet too, AMD could just release a revised CPU with updated I/O die that has DDR5 support. They really wouldn't have to change anything other than that, nothing stops them from selling DDR4 and DDR5 SKUs if they get the sales to allow it. If EPYC2 becomes extremely popular that'll allow them to do pretty much what ever they want.

 

Such a flexible approach.

 

6 minutes ago, Taf the Ghost said:

The drop-in compatibility is clever move. Seems strange in Server, but with AMD's market position, this will allow all of those Server System Designs to be reused until ~2022. They'll add in PCIe 4.0 designs as well, but, as of yet, very little is coming to PCIe 4.0 that quickly. It isn't any faster, just more total bandwidth.

HPE does server generations every 3 years and Gen 10 was mid 2017, Gen 11 is going to be 2020 ish so that's when they will update to the latest of everything possible.

[Taf the Ghost]

Just now, GoldenLag said:

i am assuming they put 2 chips close together for easy soldering process

It's about connection lengths. I also expect the pairs of Chiplets to act as a single "domain" for scheduling purposes. Basically a 4 x 4 CCX design. That's the reason for the early 4+1 rumors. These chiplets are going to be symmetric, which means they actually just cut them in half for yield reasons/not have to make a lower SKU design.

[Dylanc1500]

10 minutes ago, Taf the Ghost said:

@Dylanc1500

Someone on Reddit adjusted them enough for measurements, but it's interesting that this was clearly AMD's plan when they laid out their chiplet strategy. Though part of me really does like the 45 degree angle designs. Always just something cool about them.

Ya, I saw the dies. Something tells me when they were looking at building the Zen uarch someone looked at what IBM did and said "lets go on a similar route but with x86 and more up to date I/O and memory".

 

By the way, their chip layout looks similar to Intels knights landing chip layout.

[leadeater]

2 minutes ago, Taf the Ghost said:

It's about connection lengths. I also expect the pairs of Chiplets to act as a single "domain" for scheduling purposes. Basically a 4 x 4 CCX design. 

None of that actually matters anymore like it did with the previous generations, there's only 1 NUMA zone for this CPU and all cores or chiplets or CCX etc have equal access to all system memory. This is what the 2970WX/2990WX should have been.

[Taf the Ghost]

4 minutes ago, leadeater said:

Increasing the width of the FMAs was what I was expecting, easiest thing to do.

 

Strictly EPYC2 for now, unless Ryzen goes chiplet too, AMD could just release a revised CPU with updated I/O die that has DDR5 support. They really wouldn't have to change anything other than that, nothing stops them from selling DDR4 and DDR5 SKUs if they get the sales to allow it. If EPYC2 becomes extremely popular that'll allow them to do pretty much what ever they want.

 

Such a flexible approach.

 

HPE does server generations every 3 years and Gen 10 was mid 2017, Gen 11 is going to be 2020 ish so that's when they will update to the latest of everything possible.

A mid-cycle DDR5 version would make sense. AMD is actually hedging against the DDR5 supply for Servers that way. DDR5 is supposedly to be a much bigger technical change than previous DDR changes, so that's why I'm thinking we won't see DDR4 & 5 on the same controller dies. 

[leadeater]

5 minutes ago, Dylanc1500 said:

By the way their chip layout looks similar to Intels knights landing chip layout.

That's just on package memory though right? It's still one big ass CPU die?

[Taf the Ghost]

4 minutes ago, leadeater said:

None of that actually matters anymore like it did with the previous generations, there's only 1 NUMA zone for this CPU and all cores or chiplets or CCX etc have equal access to all system memory. This is what the 2970WX/2990WX should have been.

Well, there is still a penalty for moving from CCX to CCX, so the Domain would act as 3 other "regional" CCXs. Same with the Epyc or Threadripper now. It doesn't matter too much in the massive parallel environments of servers, but it will on things like Threadripper. Though I did originally think they were going to act as a 4-way NUMA node than a fully independent memory controller.

[Dylanc1500]

4 minutes ago, leadeater said:

That's just on package memory though right? It's still one big ass CPU die?

Yes, that's 16GB of MCDRAM and a big ass CPU die lol.

[Taf the Ghost]

@leadeater

 

Now it gets really interesting for Desktop, as there almost has to be a controller Die for it as well. Are we going to see the entire Zen 2 product stack with GPUs on them? That would explain some of the size of the Controller die. The full GPU system on the Raven Ridge APUs is about 110mm², which would fit pretty nicely on that central die. 

[Taf the Ghost]

https://twitter.com/PaulyAlcorn/status/1059945878515965952

 

Quote

Rome supports up to 4TB of memory per socket.

Would appear to be 16 slots (16 x 256 Gb) of memory can be configured for Rome. That's a lot of memory to populate. Also, with 256 Gb DIMMS, most of the system would be the memory.

[cj09beira]

2 hours ago, Taf the Ghost said:

@leadeater

 

Now it gets really interesting for Desktop, as there almost has to be a controller Die for it as well. Are we going to see the entire Zen 2 product stack with GPUs on them? That would explain some of the size of the Controller die. The full GPU system on the Raven Ridge APUs is about 110mm², which would fit pretty nicely on that central die. 

considering one of their slides was showing a 2 die config, and in the same slide the io die was symmetrical with the axis on the middle (horizontal), they might be able to cut the io die in half and use that half for threadripper, and maybe even ryzen 

[Taf the Ghost]

3 minutes ago, cj09beira said:

considering one of their slides was showing a 2 die config, and in the same slide the io die was symmetrical with the axis on the middle (horizontal), they might be able to cut the io die in half and use that half for threadripper, and maybe even ryzen 

I think Threadripper gets either 4 or 6 channel memory, so the somewhat defective dies, since it'll use the same packaging. Though I also think they probably aren't going to be socket compatible with X399. (I also expect up to 48 cores as the highest they'll go. And no more Leech dies.)

 

But I also think we're going to get lot of Semi-Custom versions of that controller die, which AMD will also use to their own ends. Those Vega Mobile parts will show up in house with Navi + HBM2 + some amount of chiplets on the other side. AMD now has a full scale Lego Blocks approach functional, so the sky is the limit.

[Taf the Ghost]

@leadeater

 

Apparently, there won't be Gen Z on Rome? Or at least not standard. AMD might have had it in the original design/some version of the Controller Die but then removed it for launch. Might actually be the Socket is the issue. Will have to keep an eye on it.