16-Core Ryzen 9 3000 Series ES Sample spotted & Zen 2 is a Memory OC Beast, DDR4-5000 Possible! (Updated)

[S w a t s o n]

1 hour ago, cj09beira said:

that would only be true if they can afford to delay zen 3, which i would not advise to, 

They wont be delaying Zen3 because it's in Perlmutter and may or may not be in Frontier (could be Zen4 or semicustom)

There is no Zen2+, there wont ever be a Zen2+. People like Lisa and Forrest Norrod have very much confirmed the roadmap. The reasons being given dont make much sense from AMD's strategy. They dont want to be producing more than 1 architecture at a time if they dont have to, that's the strength of their chiplet strategy.

[schwellmo92]

8 hours ago, S w a t s o n said:

6nm wont be out until after 5nm, long after Zen3 exists. It's a bit odd but 6nm is 7nm++ meant for people that want the best perf on N7 design rules. AMD wont be waiting on nodes, they know Intel's 7nm is coming along well

Actually incorrect, the N6 is actually a worse node than N7+ in terms of density, power, performance. The advantage to N6 is no design work to move from N7 and cheaper to manufacture.

[Chett_Manly]

I don't know if I will buy it if it doesn't have a 5 ghz+ boost clock. Truthfully I don't need the upgrade, and it may even be hard to notice for me. So if it doesn't scratch that awesome itch, and let me see 5000 mhz under load, going to be a hard sell.

[Derangel]

29 minutes ago, Chett_Manly said:

I don't know if I will buy it if it doesn't have a 5 ghz+ boost clock. Truthfully I don't need the upgrade, and it may even be hard to notice for me. So if it doesn't scratch that awesome itch, and let me see 5000 mhz under load, going to be a hard sell.

5Ghz boost on a 16 core CPU was always a pipe dream. If they can get the release model out at a 4.5Ghz boost then maybe 5Ghz via OC would be possible with good cooling but I'm not sure if I'd even count on that.

[MeatFeastMan]

https://www.tomshardware.com/news/amd-x570-chipset-biostar-racing-x570gt8,39324.html

 

DDR4 4000 is the realistic number as confirmed by this article. Woohoo, AMD looks to have delivered! This could be the breakthrough we were all hoping for. A good sign for the rest of Zen2.

 

5000 was always unrealistic for the memory side. DDR4 4000 is good enough for me, that means the memory has been upped by 400mhz then (Because most boards went up to 3600 on second gen. Although it could be 4200, 4400 if that board is a lower end x570). Thankfully that means my 3466 2x16gb kit will just about work. £300 gamble paid off.

[GoldenLag]

5 minutes ago, MeatFeastMan said:

5000 was always unrealistic for the memory side. DDR4 4000 is good enough for me, that means the memory has been upped by 400mhz then (Because most boards went up to 3600 on second gen. Although it could be 4200, 4400 if that board is a lower end x570). Thankfully that means my 3466 2x16gb kit will just about work. £300 gamble paid off.

I still dont see why we care about faster memmory as general consumers......

 

3000mhz - 3600mhz is more than enough for 16 cores. Beyond that there is little gain to be had. 

[S w a t s o n]

10 hours ago, schwellmo92 said:

Actually incorrect, the N6 is actually a worse node than N7+ in terms of density, power, performance. The advantage to N6 is no design work to move from N7 and cheaper to manufacture.

Actually incorrect, show me a source saying otherwise. N6 is N7+ with an additional EUV layer. It's literally 7nm++ and is meant to be the final most cost effective version of 7nm. The use of EUV is to reduce defects and increase yield and speed of wafer processing, using EUV for an additional layer helps with this.

[schwellmo92]

18 minutes ago, S w a t s o n said:

Actually incorrect, show me a source saying otherwise. N6 is N7+ with an additional EUV layer. It's literally 7nm++ and is meant to be the final most cost effective version of 7nm. The use of EUV is to reduce defects and increase yield and speed of wafer processing, using EUV for an additional layer helps with this.

https://www.anandtech.com/show/14290/tsmc-most-7nm-clients-will-transit-to-6nm

 

Now your source?

[S w a t s o n]

1 minute ago, schwellmo92 said:

https://www.anandtech.com/show/14290/tsmc-most-7nm-clients-will-transit-to-6nm

 

Now your source?

Want to point out what exactly you're quoting in there?

My source is literally every semiconductor site and forum explaining how EUV is actually used to relax design rules on the BEOL metal layers and that any 7nm design should slot into 7nm+ no problem

[S w a t s o n]

5 minutes ago, schwellmo92 said:

https://www.anandtech.com/show/14290/tsmc-most-7nm-clients-will-transit-to-6nm

 

Now your source?

Pretty sure the article writer has made an assumption based on TSMC assuring N6 has the same design rules. It was expected for 7nm+. I'm reading the ACTUAL sources that anadtech article is quoting from and they never mention 7nm+ being different design rules
https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/tsmc-technology-symposium-report
https://www.tsmc.com/tsmcdotcom/ExtIRListingQuarterlyAction.do?action=listByYearAndQuarter&year=2019&theQuarter=1&language=E#

[The Benjamins]

https://videocardz.com/newz/biostar-leaks-its-own-x570-racing-gt8-motherboard

 

Biostar leaked its x570 motherboard that has a 4000mhz ram profile. it also has 1 M.2 PCIe gen4 x4 from CPU and 2 M.2 PCIe gen4 x4 from chipset.

 

That means the Chipset supprots PCIe gen4 which means its link is at least 2x faster. yay for more M.2

[S w a t s o n]

10 minutes ago, schwellmo92 said:

https://www.anandtech.com/show/14290/tsmc-most-7nm-clients-will-transit-to-6nm

 

Now your source?

Here's what TSMC says.

2 minutes ago, S w a t s o n said:

https://www.tsmc.com/tsmcdotcom/ExtIRListingQuarterlyAction.do?action=listByYearAndQuarter&year=2019&theQuarter=1&language=E#

Quote

Now I'll talk about the ramp up of N7 and N7+ and introduction of N6. We are seeing strong tape-out activities at N7, which include HPC,IoT and automotive. Meanwhile, our N7+, which adopts EUV for a few critical layers, has already started volume production now. Theyield rate is comparable to N7. We reaffirm N7 and N7+ will contribute more than 25% of our wafer revenue in year 2019.As we continue to improve our 7-nanometer technology and by leveraging the EUV learning from N7+, we now introduce N6 process. N6has 3 major advantages. First, N6 have 100% compatible design rules with N7, which allow customer to directly migrate from N7-baseddesign, which substantially shortened time-to-market. Second, N6 can deliver 18% higher logical density as compared to N7 and providecustomer with a highly competitive performance-to-cost advantage. Third, N6 will offer shortened cycle time and better defect density.Risk production of N6 is scheduled to begin in first quarter year 2020 with volume production starting before the end of 2020.

N6=N7, nothing about N7+ not being compatible on N7 design rules

[Taf the Ghost]

18 minutes ago, The Benjamins said:

https://videocardz.com/newz/biostar-leaks-its-own-x570-racing-gt8-motherboard

 

Biostar leaked its x570 motherboard that has a 4000mhz ram profile. it also has 1 M.2 PCIe gen4 x4 from CPU and 2 M.2 PCIe gen4 x4 from chipset.

 

That means the Chipset supprots PCIe gen4 which means its link is at least 2x faster. yay for more M.2

PCIe x16 slot is also staying PCIe 3.0. We can probably expect that from most motherboards. The extra M.2 PCIe slots will be the fun stuff.

[The Benjamins]

2 minutes ago, Taf the Ghost said:

PCIe x16 slot is also staying PCIe 3.0. We can probably expect that from most motherboards. The extra M.2 PCIe slots will be the fun stuff.

where do you see the PCIe slot is staying 3.0? I see it saying there are 3 PCIe slots.

 

it is odd though that the M.2 slots still say 32Gbps, when it it was 4.0 at 4x it would be 64Gbps.

[Taf the Ghost]

19 minutes ago, S w a t s o n said:

Here's what TSMC says.

N6=N7, nothing about N7+ not being compatible on N7 design rules

N6 is N7 with EUV and exists as a cost-effective move for those that made SoCs on N7. As of right now, there's no N6 HPC version that's known, so AMD won't have any CPU cores on the node. It could end up being used for the I/O die, but we don't know exactly the tolerances needed for that yet.

 

AMD is going Zen2 this year, then Zen3 next year on N7+ (EUV).  Zen3 will be here pretty soon. Soon enough that AMD will be deploying a Zen3 based Super Computer H2 2020. Zen2 is releasing a little late and Zen3 will come a little early. At least for some segments.

[S w a t s o n]

6 minutes ago, Taf the Ghost said:

N6 is N7 with EUV and exists as a cost-effective move for those that made SoCs on N7. As of right now, there's no N6 HPC version that's known, so AMD won't have any CPU cores on the node. It could end up being used for the I/O die, but we don't know exactly the tolerances needed for that yet.

  

AMD is going Zen2 this year, then Zen3 next year on N7+ (EUV).  Zen3 will be here pretty soon. Soon enough that AMD will be deploying a Zen3 based Super Computer H2 2020. Zen2 is releasing a little late and Zen3 will come a little early. At least for some segments.

TSMC has stated that "complex" 7nm chips will be moving on to 7nm+ which we all knew. When they said "most 7nm customers will move to 6nm" they definitely meant N7 SOC moving to N6

 

And yea Perlmutter is looking to be nice

[Taf the Ghost]

3 minutes ago, The Benjamins said:

where do you see the PCIe slot is staying 3.0? I see it saying there are 3 PCIe slots.

 

it is odd though that the M.2 slots still say 32Gbps, when it it was 4.0 at 4x it would be 64Gbps.

Hmm... guess I read it wrong the first time. Though these look to be wired identically to the previous one, so I wouldn't expect PCIe 4.0 on the slots.

 

Also, I don't read that as 3 M.2 slots. It's two M.2 slots. (See the Key M* marker in the X470 board for the structure they showed). The M.2 slots are wired for PCIe 4.0, but I think they only work with PCIe 3.0 x4 NVMes. The PCIe 4.0 NVMe drives might not be supported at launch. (Pretty sure those are all high-end Server parts at this point and might be keyed differently?)  But there is at least a NVMe supporting M.2 slot coming off the PCH, which is interesting.

[The Benjamins]

2 minutes ago, Taf the Ghost said:

Hmm... guess I read it wrong the first time. Though these look to be wired identically to the previous one, so I wouldn't expect PCIe 4.0 on the slots.

 

Also, I don't read that as 3 M.2 slots. It's two M.2 slots. (See the Key M* marker in the X470 board for the structure they showed). The M.2 slots are wired for PCIe 4.0, but I think they only work with PCIe 3.0 x4 NVMes. The PCIe 4.0 NVMe drives might not be supported at launch. (Pretty sure those are all high-end Server parts at this point and might be keyed differently?)  But there is at least a NVMe supporting M.2 slot coming off the PCH, which is interesting.

normally X*(slot info) X means the number of slots. so I see it as 1 of one slot type, and 2 of the other slot type.

 

we will see once it officially out, I am expecting the chipset to be linked by PCIe 4.0 so we sould have 2x the bandwidth to the chipset on x570.

[Taf the Ghost]

2 minutes ago, S w a t s o n said:

TSMC has stated that "complex" 7nm chips will be moving on to 7nm+ which we all knew. When they said "most 7nm customers will move to 6nm" they definitely meant N7 SOC moving to N6

 

And yea Perlmutter is looking to be nice

N6 looks to be the 2020 node for most mobile SoCs. 5nm probably won't be ready for their launch cycles that year, even if they're taking Designs right now for it.  However, that's for mobile SoCs. AMD is going to be moving rapidly down the nodes that TSMC offers. Zen4 is 2021 on DDR5 from what we know right now.

[S w a t s o n]

3 minutes ago, Taf the Ghost said:

N6 looks to be the 2020 node for most mobile SoCs. 5nm probably won't be ready for their launch cycles that year, even if they're taking Designs right now for it.  However, that's for mobile SoCs. AMD is going to be moving rapidly down the nodes that TSMC offers. Zen4 is 2021 on DDR5 from what we know right now.

Definitely agree here too, honestly AMD could have Zen 3 on 5nm if they REALLY wanted to but because of the aggressive timeline (and risk) they wont.

 

N6 in 2020 for flagships I'm not sure about. Maybe production but not in a 2020 phone, 2021 phone sure

[Taf the Ghost]

6 minutes ago, S w a t s o n said:

Definitely agree here too, honestly AMD could have Zen 3 on 5nm if they REALLY wanted to but because of the aggressive timeline (and risk) they wont.

 

N6 in 2020 for flagships I'm not sure about. Maybe production but not in a 2020 phone, 2021 phone sure

As long as they hit full production ramp by May, the node is ready for Fall releases. We can thank Apple for understanding that cadence, haha. Apple should be on 7EUV for their releases this year.

 

Zen4 on 5nm with "advanced packaging" is 2021. We know that because of TSMC's earnings call. They didn't technically say AMD, but "HPC customer" when that's pretty much just AMD made that pretty clear. Now, what the I/O dies are on, that's an open question.

[S w a t s o n]

1 minute ago, Taf the Ghost said:

As long as they hit full production ramp by May, the node is ready for Fall releases. We can thank Apple for understanding that cadence, haha. Apple should be on 7EUV for their releases this year.

 

Zen4 on 5nm with "advanced packaging" is 2021. We know that because of TSMC's earnings call. They didn't technically say AMD, but "HPC customer" when that's pretty much just AMD made that pretty clear. Now, what the I/O dies are on, that's an open question.

I dont think Apple will be going to N6 actually, they will want N5 imo. Apple doesnt care about cost effectiveness when it comes to their SOC's

[Taf the Ghost]

2 minutes ago, S w a t s o n said:

I dont think Apple will be going to N6 actually, they will want N5 imo. Apple doesnt care about cost effectiveness when it comes to their SOC's

For their leading edge products, I agree. For their more trailing edge ones, they might. But TSMC clearly thinks 6nm will be pretty popular, though it's one of those "out of the blue" nodes, which is sort of strange unto itself.

[schwellmo92]

8 hours ago, S w a t s o n said:

Here's what TSMC says.

N6=N7, nothing about N7+ not being compatible on N7 design rules

N6 = 18% density over N7

N7+ = 20% density over N7

 

You can read between the lines. Why would TSMC be expecting N7 customers to migrate to N6 instead of N7+? N7+ is denser.

[S w a t s o n]

15 minutes ago, schwellmo92 said:

N6 = 18% density over N7

N7+ = 20% density over N7

 

You can read between the lines. Why would TSMC be expecting N7 customers to migrate to N6 instead of N7+? N7+ is denser.

No you can't read between the lines that N7+ somehow has magically different design rules from that information. N7+ is mostly going to be used for high power chips, N6 for lower power. N6 also has up to 4 more EUV layers than N7+ (thought it was just 1, anandtech got that wrong too) which again reduces defects and processing time, this translates to reduced costs.

 

 

So to be clear, AMD is on 7nm HPC, Apple and Huawei are on 7nm SOC. 6nm is going to be mostly SOC. 7nm+ should support both but will be targeted for HPC mostly