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der8auer RYZEN THREADRIPPER DELIDDING!!

4 minutes ago, TOMPPIX said:

surprise!!!

Now put it back together :P

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This is odd, but this is the first AMD Ryzen Threadripper video on my video feed:

Der8auer had done that, and it is broken. And then this is were I have made this as a headline news right now..

UPDATE: It may be an engineering sample.

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So this confirms TR and eypc is soldered.

I am very surprised by the 4 dies, and why would they keep 2 not used dies on it.

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Interesting

That looks like an epyc die package though, it has 4 Zeppelin dies.

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Now put that under a high powered microscope, and see if there any are hidden messages.

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dat german.

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Well, it looks as if AMD is preparing for cpus with up to 32c/64t in that case. With Ryzen they basically have the same configs and are just selecting the best dies for the top tier models and reuse imperfect dies for the smaller models.

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26 minutes ago, ScratchCat said:

Interesting

That looks like an epyc die package though, it has 4 Zeppelin dies.

Salvaged Epyc dies, that can also clock better than Epyc.

Glad they're well soldered as well. Not long until reviews now.

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30 minutes ago, The Benjamins said:

So this confirms TR and eypc is soldered.

I am very surprised by the 4 dies, and why would they keep 2 not used dies on it.

At a guess, it's because even with their yields they have plenty of completely dead dies and the EPYC IHS is designed to have 4 under it. So they either make fake ones out of plastic and hope that it doesn't deform during use or just toss the dead dies on there. Alternatively it may have something to do with Infinity Fabric routing needing a die there even if the die isn't used. They could have redesigned the IF pattern, but that may have required an entirely new socket rather than a minor revision to EPYC's.

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2 minutes ago, tom_w141 said:

Reviews would be 10/08 right? Assuming NDA is until launch

Might be then yes. Unless they put reviews out earlier to help with the OEM sales, and pre-orders. Maybe NDA lists at Siggraph for details; and in stores 10th of August.

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3 minutes ago, ravenshrike said:

At a guess, it's because even with their yields they have plenty of completely dead dies and the EPYC IHS is designed to have 4 under it. So they either make fake ones out of plastic and hope that it doesn't deform during use or just toss the dead dies on there. Alternatively it may have something to do with Infinity Fabric routing needing a die there even if the die isn't used. They could have redesigned the IF pattern, but that may have required an entirely new socket rather than a minor revision to EPYC's.

ya true.

I always felt AMD could of made a new socket for TR (2000-2700 pins) but due to time and money they didn't which hurts TR on socket size. I also would like to know if a Epyc CPU can fit in a x399 board or is it keyed differently.

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1 hour ago, The Benjamins said:

I always felt AMD could of made a new socket for TR (2000-2700 pins) but due to time and money they didn't which hurts TR on socket size. I also would like to know if a Epyc CPU can fit in a x399 board or is it keyed differently.

from what i understand 2 socket epyc solutions cannot be used in single socket systems due to pci-e lanes logistics. so i personally wouldnt expect epyc to work on X399, even single socketed ones, though i may be totally wrong.

Sorry for bad Ingrish

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Oho interesting. I mean it was odd to me a bit as far as socket size for X399 yet same like Epyc but half the cores of it. So I expected two Zeppelin dies but that goes back to my odd thing.聽

But cool, solder.聽

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Wait, what? Why 4 dies instead of 2?

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2 hours ago, The Benjamins said:

So this confirms TR and eypc is soldered.

I am very surprised by the 4 dies, and why would they keep 2 not used dies on it.

AMD promised to use only balanced CCX configurations, sometimes you get dead dies, so instead of wasting everything you just disable the other and you then have less package configurations to test

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15 minutes ago, Agost said:

Wait, what? Why 4 dies instead of 2?

that was unexpected. I can't figure out why amd did that

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Either AMD went retard on using 4 die (why would you cut your revenue per wafer i half?), or for review purposes they sent out Epyc stuff rebadged as TR.

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1 minute ago, AnonymousGuy said:

Either AMD went retard on using 4 die (why would you cut your revenue per wafer i half?), or for review purposes they sent out Epyc stuff rebadged as TR.

If they went 4+4+4+4 instead of 8+8+0+0 it's going to be full facepalm. 聽Yes please I'd like to have a 4S quad core system for my desktop.

Watch the video. Only two dies are used.

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20 minutes ago, DXMember said:

AMD promised to use only balanced CCX configurations, sometimes you get dead dies, so instead of wasting everything you just disable the other and you then have less package configurations to test

ya I know that but for the fact TR is 4 channel and has 64 PCIe it only uses 4 CCXs MC and PCIe (this one could be shared by 8)

so I figured it was a 2 die config. and he said in the video that 2 of the dies are not working on TR they are dead or off.

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31 minutes ago, The Benjamins said:

ya I know that but for the fact TR is 4 channel and has 64 PCIe it only uses 4 CCXs MC and PCIe (this one could be shared by 8)

so I figured it was a 2 die config. and he said in the video that 2 of the dies are not working on TR they are dead or off.

hope they are off

looking forward for 20 core 40 thread bios mod

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1 hour ago, sazrocks said:

Watch the video. Only two dies are used.

Yes, but WHY?

Why didn't they just put 2?

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