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About bowrilla

  • Title
  • Birthday Mar 22, 1986

Contact Methods

  • Steam

Profile Information

  • Location
  • Gender
  • Biography
    Professional Indiana Jones – just whithout occult Nazis and murderous cults … and unfortunately without whips as well …
  • Occupation
    Jack of all trades


  • CPU
    Ryzen 7 2700
  • Motherboard
  • RAM
    32GB Corsair Vengeance RGB DDR4-3200
  • GPU
    Zotac 1080Ti Mini
  • Case
    Phanteks Enthoo Evolv Shift X
  • Storage
    1x Adata M.2 500GB SSD, 2x 500GB SATA SSD
  • PSU
    Corsair SF600
  • Display(s)
    Samsung 46" LED TV
  • Cooling
    Custom Loop, 280mm Black Ice Nemesis GTX, 2x Noctua NF-A14 Industrial PWM, 2x BeQuiet Silent Wings 3 140mm PWM, 1x Cryorig XT140 PWM
  • Keyboard
    Das Keyboard 4C Professional
  • Mouse
    Corsair Harpoon RGB
  • Sound
    AKG Y50BT wireless
  • Operating System
    Win10 Pro, Ubuntu 18.10

Recent Profile Visitors

1,689 profile views
  1. Zen+ is supported on X570 (but not on B550). It is a very solid CPU.
  2. The spec sheet doesn't actually even mention 4th gen Ryzen anywhere on the storage specs. B550 is PCIe 3.0 internally, whereas X570 is PCIe 4.0. Both are connected with 4 lanes but the X570 one has (in theory) double the bandwith. The first M.2 slot is always connected directly to the CPU with 4x PCIe 4.0. Always. That's Zen architecture. 16x PCIe gen 4.0 from CPU to PCIe slot 1 (GPU), 4x PCIe gen 4.0 to M.2 and 4x PCIe 4.0 to chipset. This does not change whatever board you choose. The board manufacturer might fiddle around and give you more options (i.e. giving you a BIOS option
  3. I assume the BIOS has been updated? Are there any information from EVGA in how the lanes are being split up with Cascade Lake-X? Because there are no infos in the manual on that chip. Might be a bug as well. Have you tried disabling PM1 and PU1 (actually disabling them in BIOS and removing all drives)? The fact, that you get 8x on PE1 and PE2 (to me) indicated the board is using the shared lanes (potentially). Might be a bug, might be a technical reason.
  4. Please read pages 27 and 30 in your manual: PCIe-Slot 1 (PE1) has 16 PCIe 3.0 lanes from CPU but shares 8 lanes with PCIe-Slot 2. PCIe-Slot 2 (PE2) has 8 PCIe 3.0 lanes from CPU and shares another 8 with PCIe-Slot 1. PE3 is non-functional on 16 lane CPUs PE4 is non-functional on 16 lane CPUs PE5 has 4 PCIe 3.0 lanes from PCH (chipset) PE6 has 4 PCIe 3.0 lanes from PCH (though physical 16x) and activating it will disable PM2. Kaby Lake-X: M.2 Key-M (PM1) has 4 PCIe 3.0 lanes from CPU BUT PE1 cannot be populates and enabling PM1 will disable
  5. Most (better) ASUS boards have on board temperature headers. Wether you can use it as a source to control your fan curves can probably best be checked in the respective manual. It is possible on the better boards since you can usually switch the control source for the sys fans. I'm not sure you can always set the CPU fan curve in relation to the temp probe header. P.S.: I really wonder why it's almost (!) exclusively ASUS who's adding those headers even on mid tier mainboards and the rest at best adds it on top shelf stuff. Even my ASUS B450I had one. Eh, too
  6. D5 pumps are intended for heating systems in your house pushing around water between floors. Stop fussing.
  7. In that case I'd just go for dual loop. Add another (pump) res and you have dual loops, everything separated and you can go with two different fluids. But seriously: people fuss too much about flow. What I was trying to say is: make sure both blocks are similar in terms of flow restriction. As long as you have measruable flow, the loop works. Yes, very little flow will increase temps by a few (most likely single digit) K but unless you're trying to hit record OC this will not be of any noticeable effect. To my knowledge the EK blocks (GPU and CPU) are very similar in terms of restr
  8. First, MS is actually a huge contributor in the open source community for years now. And the optimizations I'm talking about are on library and compiler level. You don't just rewrite all of it to not be forced to share it and you don't just fork it because that would exclude you potentially from future updates. There'll be research being done on how to optimize one single algorithm, how to optimize math problems and so on. It's not just Apple working on it, it's a big community. Apple is just providing a base platform. As always, Apple isn't even the first to try this. MS had some
  9. May I add that for years (and to my knowledge true for all mainstream CPUs) x86-64 is just the exposed CISC instruction set. Internally Intel Core and most likely same with AMD Zen, they are RISC. The more complex RISC instructions are being broken down into (optimized) RISC commands and then being processed. At the end of the day it all comes down to the specific chip design and the specific application. ARM heavily benefits from parallelization but when there's a library that's not very well optimized their single core performance in those tasks just tanks. See i.e. this benchmar
  10. I have such a loop. CPU + GPU are in parallel and both radiators are in parallel. You need to be aware, that by splitting up the flow you ideally get half the flow through both routes. However, differences in restriction will divide the flow asymmetrically (relative to the restriction ratio). It is also a cost factor since you need more fittings to get everything connected. Also: make sure to use actual Y splitter and not just a straight fitting with a 30° or 45° junction because that will not divide the flow symmetrically, there'll be a lot more flow going straight down the run. N
  11. The lower limit would be 120mm of radiator space for each component but you won't get great temps under stress. So get a little bit on top. I'd say 140 or 240 for one component and 280 or 360 (or more) for both. More ist better but the more radiator space you get, the less you will benefit with each step. So going from 240 to 360 will make a difference in coolant temps, going to 480 is a smaller step, going to 600 (if you could get one) or 2x480 is even less of a benefit and so on. I'd say: get what fits your case.
  12. You do not have a custom loop, the H115i is an AiO. There are ways to either jerry rig another AiO onto your GPU or to use (if available) some mounting brackets for GPUs. There are also expendable AiOs that have the option to add different blocks and or more radiators but yours is a plain regular AiO, non-expandable, probably a generic Asetek model. You can't just try and cut your way in there to add some connections since the radiator is most likely aluminium and every half decent block is copper based. Mixing those metals means galvanic corrosion. Going custom loop will mean expe
  13. There's a plethora of speech recognition APIs out there and implementations for basically all the common and often also uncommon languages you can come up with. Edit: Here's a python library supporting 8 different speech recognition engines/APIs: https://pypi.org/project/SpeechRecognition/ including MS Bing Voice Recognition. For JS there's an experimental feature in development (Web Speech API) and for nodeJS there's a ton of packages. And here's a repo with a Rust implementation of Mozilla's DeepSpeech library: https://github.com/RustAudio/deepspeech-rs
  14. You'll get easier and quicker results and you'll learn the fundamentals quicker. That's less to wrap your head around if you choose to learn C++. But half a year is not much time to learn stuff.
  15. C++ is a great language but not an easy one to learn and you better stick with one language at first. There are some ways to get python to run on Arduinos I think. Rust would be a valid alternative to C as long as there's a compiler available for the MCU of your choice - it's a lot more approachable. For science and calculations, Python is a good choice or Fortran (very popular on supercomputers at universities). In terms of first results, languages like Python, JavaScript and Ruby are easier than plain C++. Going the route with full fletched IDEs C++ gets easier to have programs w