Why do most CPUs only have 2 threads per core?

[Helpful Tech Witch]

So, most CPUs have one or two threads per CPU core, but I was wondering why there are not more CPUs with 4c/16t or 8c/32t? Some CPUs like the IBM POWER9. That CPU has 4c/16t, and seems like, though it would be expected, it would be expensive, but, like why doesn't AMD or Intel make a CPU that has 32c/128t server CPU or something. 

 

Side note, the IBM POWER9 seems to be the only CPU with 4 thread per core.

[Moonzy]

because why have more mouth when your stomach can only digest so fast?

 

would also make task scheduling more complicated than it already is

[mahyar]

well there are x86 cpus that have 4 threads per core intels xeon phi series the thing is most workload cant use those threads very good because they are weak

[Levent]

Architectural differences. If it was feasible, they would have done it. CPU you listed uses PowerPC instruction set (which is RISC) while x86 is CISC, that most likely has a major effect but I am not that technically informed to comment more.

[mahyar]

Just now, mahyar said:

well there are x86 cpus that have 4 threads per core intels xeon phi series the thing is most workload cant use those threads very good because they are weak

btw der8auer  and linus himself did videos on xeon phi!

[Helpful Tech Witch]

Just now, Levent said:

Architectural differences. If it was feasible, they would have done it. CPU you listed uses PowerPC instruction set (which is RISC) while x86 is CISC, that most likely has a major effect but I am not that technically informed to comment more.

Isn't PowerPc more optimized? Like, even if it was writen for x86, SMG would not have been able to run like it does on wii.

[mahyar]

2 minutes ago, Levent said:

Architectural differences. If it was feasible, they would have done it. CPU you listed uses PowerPC instruction set (which is RISC) while x86 is CISC, that most likely has a major effect but I am not that technically informed to comment more.

https://en.wikipedia.org/wiki/Xeon_Phi

[Levent]

1 minute ago, TheTechWizardThatNeedsHelp said:

Isn't PowerPc more optimized? Like, even if it was writen for x86, SMG would not have been able to run like it does on wii.

Optimisation usually happens on software side rather than hardware. That is only the case if hardware is being designed to run a specific software. So no.

[mariushm]

Well, i guess it's mostly for historical reasons ... and because Windows is "optimized"/"programmed" for two threads per core. The operating system's kernel would have to be tweaked and tuned and more clever algorithms would have to be written to support well more than 2 threads per core.

It can take years for some new thing to be well supported... you can see in Ryzen and Threadripper how long it took for Windows to understand the concept of CCX (core complex, chiplet with 4 cores / 8 threads) and using multiple dies to make a cpu...

 

There are rumors AMD wants to make the next AMD EPYC cpu (for servers) have 4 threads , so you'll have up to 64 cores / 256 threads ... but not sure it's gonna happen.

[Haro]

10 hours ago, TheTechWizardThatNeedsHelp said:

with 4c/16t or 8c/32t?

2 threads does allow the core to do more than one task at once, with this there will probably be some software problems with scheduling.

[BobVonBob]

2 minutes ago, TheTechWizardThatNeedsHelp said:

Isn't PowerPc more optimized? Like, even if it was writen for x86, SMG would not have been able to run like it does on wii.

"More optimized" isn't really a thing, at least not for instruction sets. x86 has more instructions, but it does individual ones slower. PowerPC and its replacement Power ISA have fewer instructions, but they do individual ones faster. Whether the reduced instruction set or the greater per-instruction capabilities are more valuable to your program depends on the program. Modern compilers generally mean that the same code on x86 and RISC end up being similarly fast without extreme edge cases.

[mahyar]

4 minutes ago, Benji said:

Well, the IBM chips, IIRC, are more for database management and interconnect systems which can handle multitasking better than usual end-user stuff. That's most likely why they have such high SMT counts. Also, the POWER9 not only has 24c SMT4 core options, but also 12c SMT8 cores, POWER10 supposedly bringing 30-core SMT8 CPZs (30C 240T).

@mahyar They aren't stand-alone CPUs that make a sense as CPUs, they are intended as accelerator cards. Due to the fact that they are x86 with a few modern extensions, they do run Windows, but horribly.

yeah earlier ones were coprocessors and used a pci-e bus to connect to system but newer ones are like normal cpus and they are used in LGA3647 socket

[LAwLz]

I think the answer becomes somewhat obvious if you know how SMT works.

 

Contrary to popular belief, SMT does not behave like having two cores would. A processor is comprised of several different units. To simplify things, imagine if your processor had a dedicated "addition" unit and a separate "subtraction" unit. If you have two threads that both need to do addition, SMT will flat out not work. You do not gain anything from having SMT in such a situation. In fact, you might even have a net negative performance effect because of the added complexity and power it uses.

However, if you just so happen to have one thread that needs to use the addition unit and one thread that needs to use the subtraction unit, an SMT enabled core will be able to schedule both tasks simultaneously on a single core, SMT will help out.

 

But SMT stops being efficient once you can reliably feed all different execution units at all time. I think that Intel has determined that for their CPU designs, going above 2 threads per core don't actually provide much benefit since they can keep all their execution units fed reliably. Going above 2 threads in such a situation will add die area which in turn makes the chips more expensive, use more heat and puts more stress on the cache (which might actually harm performance even more if you're already maxing out the cache) since you now need to store more instructions in each core's cache (so rather than having let's say 1MB of cache dedicated to the program running addition instructions, you now might only have 0,5MB for that thread, and the other 0,5MB is used by the subtraction thread).

 

Also, Intel shares their server designs with their consumer designs. They most likely save more money than they would make by designing one way that "works well enough everywhere" than the small profits they could potentially make by designing some 4 way SMT monster core that would not be useful anywhere outside of highly specialized tasks.

 

That's why Xeon Phi had 4 way SMT by the way. Because it was designed for highly parallel workloads and it was not suitable for what most people uses their computers for. They trashed that idea because it wasn't seen as profitable (enough).

[Windows7ge]

As explained above threads aren't physical cores. They basically feed the cores jobs. In certain workloads there is an appreciable gain by having more threads but in most day to day applications more physical cores can do more work than lesser cores with more threads.

 

Science and research applications though where they need to track many many simultaneous data points across a model like protein folding and the impacts of chemicals on DNA CPUs like Intel's Xeon Phi 7230 with 64C/256T can run this kind of simulation very well because of the special type of workload.

 

Meanwhile your desktop will do better with more real cores for its given type of workloads or lesser faster cores in the case of gaming.

 

It's all about the type of workload that determines which hardware will do the job best.

[igormp]

16 minutes ago, TheTechWizardThatNeedsHelp said:

So, most CPUs have one or two threads per CPU core, but I was wondering why there are not more CPUs with 4c/16t or 8c/32t? Some CPUs like the IBM POWER9. That CPU has 4c/16t, and seems like, though it would be expected, it would be expensive, but, like why doesn't AMD or Intel make a CPU that has 32c/128t server CPU or something. 

 

Side note, the IBM POWER9 seems to be the only CPU with 4 thread per core.

iirc, POWER (POWER8 in special) and SPARC where the only mainstream ISAs with STM8 (8 threads per core). Usually going for higher threads per core requires more execution units, which usually end up being a waste of space and resources for your regular user demands.

@LAwLz beat me to it and already gave a pretty good basic explanation on why that's the case.

[LAwLz]

7 minutes ago, Levent said:

Optimisation usually happens on software side rather than hardware. That is only the case if hardware is being designed to run a specific software. So no.

4 minutes ago, BobVonBob said:

"More optimized" isn't really a thing, at least not for instruction sets. x86 has more instructions, but it does individual ones slower.

Worth noting that the POWER10 chips are probably designed to run IBM software. So I wouldn't be surprised if IBM's software have played a major role in the development and design of POWER10.

 

IBM are currently VERY focused on storage and AI. Would you guess what the main features of POWER10 are? Better I/O architecture and performance in AI workloads!

 

 

8 minutes ago, mariushm said:

Well, i guess it's mostly for historical reasons ... and because Windows is "optimized"/"programmed" for two threads per core.

Even if it was the case that Windows was "optimized" for two threads per core (which it isn't), adding support for more would be rather trivial.

[Mark Kaine]

Isn't that kinda how CELL worked also? 

 

Imagine the PPE is the "core" and the SPES are the "threads" 

 

 

And now imagine the true power you would get if you had 8 or 16 or more of these "cores" on one chip... 

 

IBM were truly ahead of their time. 

 

(I could be wrong lol)

[igormp]

3 hours ago, Mark Kaine said:

Isn't that kinda how CELL worked also? 

 

Imagine the PPE is the "core" and the SPES are the "threads" 

 

And now imagine the true power you would get if you had 8 or 16 or more of these "cores" on one chip... 

 

IBM were truly ahead of their time. 

 

(I could be wrong lol)

No, the SPE units in CELL is more akin to a SIMD unit with no proper branching, but capable of doing operations of tons of data at once (basically a shitty GPU implementation).

 

Sony planned to use it as the main graphics driver, but once they've seen how shitty it was, they had to ask for nvidia for a GPU. In the end it was kinda ok and helped the GPU somewhat, since the actual GPU itself wasn't that good either.