(16core added)AMD 3000 specs! 4.7 GHZ, R9 3950x, R7 3700x, 3800x.

[schwellmo92]

3 hours ago, Origami Cactus said:

Broadwell, 14

Skylake, 14+

Kaby Lake, 14++

Coffee Lake, 14+++

And then now the 10 core part, Ice Lake?

That’s incorrect, each generation was not a new process node.

 

This is the mainstream, the HEDT/server can differ:

Broadwell/Skylake, 14nm.

Kaby Lake, 14nm+.

Coffee Lake/Refresh, 14nm++.

Comet Lake, ?

[leadeater]

55 minutes ago, Simon771 said:

Any idea if Ryzen 3000 series still have communication between CCX-es limited to 1/2 of RAM speed?

Not really known. The CCXs still exist, far as we know, but since the I/O die has the memory controllers and the chiplet dies do not the most likely clock reference is the Infinity Fabric bus. The IF could still be clocked off the memory though, all paths lead back to the I/O die so you can still sync off the IMC by way of the IF syncing off that. Everything is ultimately clocked from the Base Clock (BCLK) anyway and are just multipliers of that and ratios against other things.

 

Zen 2 Infinity Fabric is supposed to be slightly over twice as fast, "2.3x transfer rate per link (25 GT/s, up from ~10.6 GT/s)", but how exactly will be explained later.

[MeatFeastMan]

Oh boy. Intel is about to start sweating cause it looks like AMD is going to drop the bomb at E3.

https://videocardz.com/newz/amd-ryzen-9-3950x-to-become-worlds-first-16-core-gaming-cpu

 

4.7ghz, 105w tdp...maybe that proves 5ghz on the lesser 6 and 8 core chips could still happen?

[nick name]

3 minutes ago, MeatFeastMan said:

Oh boy. Intel is about to start sweating cause it looks like AMD is going to drop the bomb at E3.

https://videocardz.com/newz/amd-ryzen-9-3950x-to-become-worlds-first-16-core-gaming-cpu

 

4.7ghz, 105w tdp...maybe that proves 5ghz on the lesser 6 and 8 core chips could still happen?

I knew it would be a 3950X!  I knew it!  

 

I'm also still hoping for a 3850X.  

[RejZoR]

Only thing I'm interested in seeing reviews is to see core scaling based on load. How clock scales (drops) with number of cores under load. Since AMD didn't go into such detail for it during ComputeX.

[Stefan Payne]

4 hours ago, Simon771 said:

Any idea if Ryzen 3000 series still have communication between CCX-es limited to 1/2 of RAM speed?

They don't.

There is no reason for it as the Memory Controller is inside the I/O Die. There is the possibility of a small buffer for asyncrhouneous transfers between that.

And even if, they use higher frequency IF anyway.

[Princess Luna]

8 hours ago, Origami Cactus said:

Broadwell, 14

Skylake, 14+

Kaby Lake, 14++

Coffee Lake, 14+++

And then now the 10 core part, Ice Lake?

Intel states that Broadwell and Skylake both uses the same 14nm architecture, Kaby Lake is 14nm+ and Coffee Lake and Coffee Lake Refresh 14nm++

 

From what I understood that upcoming 10c i9 is still the same 14nm++ as Coffee Lake as well so not even another polishing to the architecture, at best a couple more hardware fixes for the newer security issues.

 

Until Intel rolls out their 10nm on desktop or maybe if 10nm does end up to mobile only then the 7nm I honestly don't see Intel being competitive until like 2022... after all 8c already seems as high as Ring Bus can still be a thing... they are going to force a 10c on the same architecture and ring bus expect it to be a monstrosity on the regards of power hunger.

[Simon771]

6 hours ago, leadeater said:

Not really known. The CCXs still exist, far as we know, but since the I/O die has the memory controllers and the chiplet dies do not the most likely clock reference is the Infinity Fabric bus. The IF could still be clocked off the memory though, all paths lead back to the I/O die so you can still sync off the IMC by way of the IF syncing off that. Everything is ultimately clocked from the Base Clock (BCLK) anyway and are just multipliers of that and ratios against other things.

 

Zen 2 Infinity Fabric is supposed to be slightly over twice as fast, "2.3x transfer rate per link (25 GT/s, up from ~10.6 GT/s)", but how exactly will be explained later.

 

2 hours ago, Stefan Payne said:

They don't.

There is no reason for it as the Memory Controller is inside the I/O Die. There is the possibility of a small buffer for asyncrhouneous transfers between that.

And even if, they use higher frequency IF anyway.

I hope you are both right, and it will go over I/O die on the CPU itself.

I watched some video on youtube, from a guy explaining how to get higher FPS in BlackDesertOnline. Basicly disabling some of it cores, so it will only use cores from single CCX. Result is obvious right away, that it does help. He used Ryzen 1700 in this test: https://www.youtube.com/watch?v=iR8ntMAxdQ0

 

Since that's the main game I play, I need to think twice before switching from my i5 8600k at 4,8GHz (-1AVX) to Ryzen 5 3600X.

[Origami Cactus]

29 minutes ago, Simon771 said:

 

I hope you are both right, and it will go over I/O die on the CPU itself.

I watched some video on youtube, from a guy explaining how to get higher FPS in BlackDesertOnline. Basicly disabling some of it cores, so it will only use cores from single CCX. Result is obvious right away, that it does help. He used Ryzen 1700 in this test: https://www.youtube.com/watch?v=iR8ntMAxdQ0

 

Since that's the main game I play, I need to think twice before switching from my i5 8600k at 4,8GHz (-1AVX) to Ryzen 5 3600X.

That is not a sensible switch IMO. You already have a really good cpu, the 3600x would only be a few percent faster, so i would just keep your current cpu until ryzen 4000, or get a 3700x.

 

[Unixsystem]

7 hours ago, schwellmo92 said:

That’s incorrect, each generation was not a new process node.

 

This is the mainstream, the HEDT/server can differ:

Broadwell/Skylake, 14nm.

Kaby Lake, 14nm+.

Coffee Lake/Refresh, 14nm++.

Comet Lake, ?

While you are correct I'm pretty sure most people are just adding more pluses to poke fun at Intel, not because anyone thinks it's an official product designation. 

 

As far as I can remember, even Kaby Lake wasn't on any original roadmaps, it was just supposed to go 14nm Skylake -> 10nm Cannonlake (Icelake?). While stagnation isn't a good thing for anyone, it is pretty comical just how long they've been milking 14nm.

[cj09beira]

2 hours ago, Simon771 said:

 

I hope you are both right, and it will go over I/O die on the CPU itself.

I watched some video on youtube, from a guy explaining how to get higher FPS in BlackDesertOnline. Basicly disabling some of it cores, so it will only use cores from single CCX. Result is obvious right away, that it does help. He used Ryzen 1700 in this test: https://www.youtube.com/watch?v=iR8ntMAxdQ0

 

Since that's the main game I play, I need to think twice before switching from my i5 8600k at 4,8GHz (-1AVX) to Ryzen 5 3600X.

you can always simply limit the game to the first 8 threads (or 6 if its a 12 core), though gaming performance is the biggest thing that is still up in the air 

[Settlerteo]

Spoiler

Ryzen 9 3950x

Hope you all saw that 16 core beast reveal. Don't need to make a new post about it.!!!

[leadeater]

All the important information everyone needs to know or has asked about Zen 2. More detailed information to come at later more specialized industry events.

 

Quote

On these chiplets are two groups of four-cores arranged in a ‘core complex’, or CCX, which contains those four cores and a set of L3 cache – the L3 cache is doubled for Zen 2 over Zen 1.

Confirmation of 4 core CCXs per chiplet.

 

Quote

The IO die for the EPYC Rome processors is built on TSMC’s 14nm process, however the consumer processor IO dies (which are smaller and contain fewer features) are built on the Global Foundries 12nm process.

Ryzen and EPYC use different I/O dies, my speculation here is expect TR to use TSMC 14nm.

 

Edit: Correction to above, Ryzen 12nm GloFo I/O die and EPYC 2 14nm GloFo I/O die.

 

Quote

The six and eight-core processors have one chiplet, while above this the parts will have two chiplets, but in all cases the IO die is the same.

The second chiplet is only added when the extra cores are required, there is no balancing or spreading of cores across dies for core counts below that of a single chiplet. Active cores will likely be even across dies.

 

Quote

As with the consumer processors, no chiplet can communicate directly with each other – each chiplet will only connect directly to the central IO die.

All roads lead to Rome the I/O die. Adjacent chiplets are not linked.

 

Trace highway to hell

 

Quote

With the move to Zen 2, we also move to the second generation of Infinity Fabric. One of the major updates with IF2 is the support of PCIe 4.0, and thus the increase of the bus width from 256-bit to 512-bit.

 

Overall efficiency of IF2 has improved 27% according to AMD, leading to a lower power per bit. As we move to more IF links in EPYC, this will become very important as data is transferred from chiplet to IO die.

To Infinity and Beyond!

 

Quote

One of the features of IF2 is that the clock has been decoupled from the main DRAM clock. In Zen and Zen+, the IF frequency was coupled to the DRAM frequency, which led to some interesting scenarios where the memory could go a lot faster but the limitations in the IF meant that they were both limited by the lock-step nature of the clock. For Zen 2, AMD has introduced ratios to the IF2, enabling a 1:1 normal ratio or a 2:1 ratio that reduces the IF2 clock in half.

So the IF is still referenced to the memory clock but the ratio is adjustable.

 

 

 

 

Source: https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome (happy reading as there is WAY more information than I posted).

[GoldenLag]

3 minutes ago, leadeater said:

Ryzen and EPYC use different I/O dies, my speculation here is expect TR to use TSMC 14nm.

wasnt Rome confirmed to be using 14nm glofo. 

 

sounds a bit unlikely they would be making another IO die. tho not unthinkable since the 14nm die for Rome is huge and probably quite costly. 

[leadeater]

1 minute ago, GoldenLag said:

wasnt Rome confirmed to be using 14nm glofo. 

 

sounds a bit unlikely they would be making another IO die. tho not unthinkable since the 14nm die for Rome is huge and probably quite costly. 

From memory the specific statement was that GloFo will still be used for I/O dies, no statement was made about single source or only one I/O die design.

[GoldenLag]

Just now, leadeater said:

From memory the specific statement was that GloFo will still be used for I/O dies, no statement was made about single source or only one I/O die design.

that is true, in the end it will be about cost. there was talk of AMD using TSMC packaging due to cost. that was untill we knew Rome IO was 14nm glofo. 

 

could very much be possible that Threadripper will actually use a different IO die alltogether and a different substrate

[leadeater]

7 minutes ago, GoldenLag said:

that is true, in the end it will be about cost. there was talk of AMD using TSMC packaging due to cost. that was untill we knew Rome IO was 14nm glofo. 

Rome I/O die is 14nm TSMC though, that's from AMD press information given out. I don't actually find it that surprising considering the number of IF link PHY interfaces the I/O die needs and how many wouldn't be used on Ryzen, also the much larger amount of PCIe lanes. If they were the same I/O die Ryzen would technically have 128 PCIe lanes, that doesn't sound bad to me though lol. The big I/O die is just too large though for Ryzen, might not have even been able to get a single chiplet on  the package.

 

Interesting comment from the AMD engineering team that I took note of was that initially Zen 2 wasn't thought to be able to cater to desktop as they expected the clock decrease caused by going to 7nm to be such that it would not suit that use case. They managed to get the clock up high enough. That does make me wonder what Ryzeen 3000 would have looked like in that situation, possibly non chiplet released later on a more mature 7nm design iteration.

[GoldenLag]

2 minutes ago, leadeater said:

Rome I/O die is 14nm TSMC though,

is it?

 

 

shit, i guess i lost that piece of info that was going out. up untill now i thought it was glofo. 

3 minutes ago, leadeater said:

The big I/O die is just too large though for Ryzen, might not have even been able to get a single chiplet on  the package.

that is very true. 

 

 

one thing that would be interesting with future iterations of Zen is favoring IF links to the chipset instead of the standard PCIe links. we know it can communicate over the same links through the implementations in GPUs. but i suspect that isnt comming for SP3, TR4 or AM4 any time soon

[leadeater]

@GoldenLag Oh FFS think you were on the money

 

 

Ian update your article damn it!

[GoldenLag]

2 minutes ago, leadeater said:

@GoldenLag Oh FFS think you were on the money

 

 

Ian update your article damn it!

ayy, my dumb ass got something correct for once. 

 

though still very likely that they could decide to do it at TSMC with threadripper just to cut some costs. because it will need a new IO die

[leadeater]

2 minutes ago, GoldenLag said:

one thing that would be interesting with future iterations of Zen is favoring IF links to the chipset instead of the standard PCIe links. we know it can communicate over the same links through the implementations in GPUs. but i suspect that isnt comming for SP3, TR4 or AM4 any time soon

That US government contract for the next big super computer is a custom Zen design based on Zen 3 and will have that IF link capability between GPUs and CPU, AMD would not confirm if that would also be found on EPYC 3.

[leadeater]

2 minutes ago, GoldenLag said:

ayy, my dumb ass got something correct for once. 

Usually internet comments are utter garbage, not this time . Glad I bothered to scroll down to them.

[TOMPPIX]

 

[GoldenLag]

Just now, leadeater said:

That US government contract for the next big super computer is a custom Zen design based on Zen 3 and will have that IF link capability between GPUs and CPU, AMD would not confirm if that would also be found on EPYC 3.

oh, very nice. 

 

 

AMD is very happy to do custom designs, and with the communication protocols and implementations of IF have made them very flexible. 

 

IF based SSDs would be fun, but i dont think we will ever see AMD in a position of creating something like that. unless they get very comfy with Samsung

[leadeater]

1 minute ago, GoldenLag said:

IF based SSDs would be fun, but i dont think we will ever see AMD in a position of creating something like that. unless they get very comfy with Samsung

That stuff is all coming under the Gen-Z technology ark, also no sure when actual in market implementation of that will exist. That will be used for storage, memory, GPUs etc. All exciting future tech stuff, maybe too future for my liking.