(16core added)AMD 3000 specs! 4.7 GHZ, R9 3950x, R7 3700x, 3800x.

[GoldenLag]

Just now, leadeater said:

All exciting future tech stuff, maybe too future for my liking.

very much so, but its good to see AMD having potensial. with Intel entering the graphics scene and 10nm finally getting along, this is going to some very exciting years

[Stefan Payne]

...and Wendels Take on it, wich show many of the Slides @leadeater posted a bit earlier...

 

And @leadeater look at 4:25min (or so)

That CLWB (Generic) Instruction, write back the line from any core or cache in the system.

 

Example:
flush dirty data to NVDIMMs for persistance sounds interesting.

Might they mean something like Optane?? Or do I misinterpret something?

[Stefan Payne]

13 minutes ago, GoldenLag said:

IF based SSDs would be fun, but i dont think we will ever see AMD in a position of creating something like that. unless they get very comfy with Samsung

They just need to ask someone that does Server SSD Controller.

There will be someone will make it...

The real Question is: Is it worth it? Does it give any benefit? Or is the advantage just not worth it...

[GoldenLag]

Just now, Stefan Payne said:

The real Question is: Is it worth it? Does it give any benefit? Or is the advantage just not worth it...

IF has a lot bandwidth in the right implementations, so it could very much be worth it. 

 

SSDs have no problem going higher on speed

[leadeater]

13 minutes ago, Stefan Payne said:

...and Wendels Take on it

lol he made the same all roads lead to Rome joke I did 

[Stefan Payne]

2 minutes ago, leadeater said:

lol he made the same all roads lead to Rome joke I did 

Yes, he did

And what's your take on 

CLWB (Generic) Instruction, write back the line from any core or cache in the system.

 

Example:
flush dirty data to NVDIMMs for persistance sounds interesting.

Might they mean something like Optane?? Or do I misinterpret something?

[leadeater]

15 minutes ago, Stefan Payne said:

Yes, he did

And what's your take on 

CLWB (Generic) Instruction, write back the line from any core or cache in the system.

 

Example:
flush dirty data to NVDIMMs for persistance sounds interesting.

Might they mean something like Optane?? Or do I misinterpret something?

It's more to do with being able to properly utilize persistent storage that is extremely fast like NVDIMMs. The I/O path in operating systems for persistent storage is quite different to non persistent memory which has rather large latency impact. Problems you only face when you go REALLY fast.

 

https://danluu.com/clwb-pcommit/ (About Intel CLWB but same thing)

[Trixanity]

@leadeater

There's indeed a lot of interesting bits in the Anandtech article. For example the new Windows scheduler updates (latest Windows 10 update) that basically schedules threads to per CCX (I guess finally) for all Zen products (gen 1 through 3). In other words it'll fill up a CCX before moving onto the next. I think that's another reason why they want to avoid multi-die (other than price) as much as possible so they don't have to split threads across CCXs and CCDs more than necessary. <8 core SKUs with single CCDs will help facilitate that.

They also enable faster clock ramp ups on gen 3 and claims it's down to 1-2 ms (although that sounds crazy when compared to Intel Speed Shift which is advertised as around 15 ms I believe) versus 30 ms previously. Sadly it's not backwards compatible for whatever reason (not sure if technical or artificial - sounds like the former).

 

Infinity Fabric is now a lot faster (double the bus width due to PCIe 4.0) and 27% more efficient. I really do wish they'd use this to get Zen 2 APUs out the door faster with a Navi chiplet in place of a second CCD although I'm not sure what can be accomplished if it's limited to 80 mm^2. Alas, I guess we're stuck with monolithic for now.

 

Also, let's rejoice in that AMD has (supposedly) provided full hardware security hardening for the known vulnerabilities.

 

Edit: they might also want to provide an updated memory controller for the APUs anyway. Reason being they could use LPDDR4 memory support for mobile and since they use the same die for gen 1 and 2 it sounds likely they'll want to do the same for gen 3. However they might still not do that despite the power efficiency gains.

[porina]

16 minutes ago, Trixanity said:

Infinity Fabric is now a lot faster (double the bus width due to PCIe 4.0) and 27% more efficient.

I saw the efficiency bit but didn't see the "faster" bit. Charts seem to show same 32B/cycle as current for IF, which is still a bandwidth concern to me.

[Trixanity]

5 minutes ago, porina said:

I saw the efficiency bit but didn't see the "faster" bit. Charts seem to show same 32B/cycle as current for IF, which is still a bandwidth concern to me.

Maybe my understanding of it is wrong but wouldn't it stand to reason that double the width and if we assume the same frequency that it would be faster? However frequency should be higher as well. I did not see the 32B/cycle thing though.

[porina]

11 minutes ago, Trixanity said:

Maybe my understanding of it is wrong but wouldn't it stand to reason that double the width and if we assume the same frequency that it would be faster? However frequency should be higher as well. I did not see the 32B/cycle thing though.

https://www.hexus.net/tech/news/cpu/131549-the-architecture-behind-amds-zen-2-ryzen-3000-cpus/

2nd to bottom chart shows 32B/cycle.

 

But...

 

Quote

One of the major updates with IF2 is the support of PCIe 4.0, and thus the increase of the bus width from 256-bit to 512-bit.

https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/11

 

256-bit is 32 byte, so if it is 512-bit wide that would be a nice improvement.

 

These appear to be in conflict with each other. Wait, no they're not, I see it now. The link between IF and IO hub is 64B/cycle, but not the rest.

[Trixanity]

25 minutes ago, porina said:

https://www.hexus.net/tech/news/cpu/131549-the-architecture-behind-amds-zen-2-ryzen-3000-cpus/

2nd to bottom chart shows 32B/cycle.

 

But...

 

https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/11

 

256-bit is 32 byte, so if it is 512-bit wide that would be a nice improvement.

 

These appear to be in conflict with each other. Wait, no they're not, I see it now. The link between IF and IO hub is 64B/cycle, but not the rest.

Yeah I see what you mean. Looks a bit weird that the byte/cycle differs between the various blocks. I guess there is a reason behind the madness. I think if nothing else we'll hear more about how it works on 7/7 or if not then, it'll be at the Hot Chips presentation. It sounds like AMD wants to hold back info even at launch so that they can drop some bombs at Hot Chips but maybe I misunderstood that part.

 

Now that I look at it perhaps it's because of the data fabric between the IOD and CCD. If I understand it correctly, the double width enables it to have a 64B/cycle link to the data fabric from the IO hub and then 32B/cycle link to each CCD. The single CCD packages will not get an extra data fabric link so as to keep it even between single and double CCD packages. So basically the double width facilitates double CCD packages with no cost to bandwidth. So that's how you get 16 cores on AM4 with two chiplets with plenty bandwidth. However the bandwidth should still be higher through better memory support but not double in that sense (depending on how you look at it). We'll see how it translates to real world performance in the reviews.

 

Edit: here's the pictures for those interested:

Spoiler

Spoiler

 

[wasab]

Does this mean that AMD has retaken the performance crown from Intel? In single thread it is certainly on par. In multithread, Intel is completely outmatch. 

[Stefan Payne]

1 hour ago, Trixanity said:

I really do wish they'd use this to get Zen 2 APUs out the door faster with a Navi chiplet in place of a second CCD

If they do that, they'd integrate the GPU into the I/O Die.

And remember, APUs traditionally have half the PCIe Lanes of the CPUs in total.

The CPUs have 32 Lanes, of wich 20+4 are usable, the APUs only have 16 Lanes, 4 for the chipset and for compatibility reasons 4 for NVME (or 2PCie + 2SATA)...

And make that a bit bigger and add the CPU Die next to it.

 

But maybe the APU will be Monolithic as it has to be cheap...

[cj09beira]

1 minute ago, Stefan Payne said:

If they do that, they'd integrate the GPU into the I/O Die.

And remember, APUs traditionally have half the PCIe Lanes of the CPUs in total.

The CPUs have 32 Lanes, of wich 20+4 are usable, the APUs only have 16 Lanes, 4 for the chipset and for compatibility reasons 4 for NVME (or 2PCie + 2SATA)...

And make that a bit bigger and add the CPU Die next to it.

 

But maybe the APU will be Monolithic as it has to be cheap...

problem is that 4 cores will be too little for an new apu, they need more than that at the very least 6 cores, and they dont really have a good way of doing that without going directly to 8 cores, adding a gpu next to it on the same die would be too expensive, keeping it in chiplets is much better, then all they need is a new io die which by now 14nm is cheap,

for the gpu die they can use the smaller discreet gpu they will make as long as they prepare for it,

the pcie limitation is a silly limitation hopefully this time it will have the full 32 lanes 

[Stefan Payne]

1 minute ago, cj09beira said:

problem is that 4 cores will be too little for an new apu, they need more than that at the very least 6 cores, and they dont really have a good way of doing that without going directly to 8 cores, adding a gpu next to it on the same die would be too expensive, keeping it in chiplets is much better, then all they need is a new io die which by now 14nm is cheap,

for the gpu die they can use the smaller discreet gpu they will make as long as they prepare for it,

the pcie limitation is a silly limitation hopefully this time it will have the full 32 lanes 

Problem:
That would be way too expensive to manufacture...

 

But lets wait and see how Renoir really looks like. And if it has more than 4 Cores..

[Trixanity]

5 minutes ago, Stefan Payne said:

If they do that, they'd integrate the GPU into the I/O Die.

And remember, APUs traditionally have half the PCIe Lanes of the CPUs in total.

The CPUs have 32 Lanes, of wich 20+4 are usable, the APUs only have 16 Lanes, 4 for the chipset and for compatibility reasons 4 for NVME (or 2PCie + 2SATA)...

And make that a bit bigger and add the CPU Die next to it.

 

But maybe the APU will be Monolithic as it has to be cheap...

The problem I see with integrating it into the IO die is the process node. Until they use some packaging technology to use different nodes at once it would be problematic unless they intend to go forward with a 7nm IO+graphics die.

 

Isn't the APU lane problem somewhat artificial to reduce complexity and/or area? I haven't seen someone ever fully explain why the lanes are cut in half for APUs.

 

Personally I would still bet on monolithic for this generation. I could imagine them trying to go full chiplet in the next generation or the one after.

[porina]

1 hour ago, Trixanity said:

Now that I look at it perhaps it's because of the data fabric between the IOD and CCD. If I understand it correctly, the double width enables it to have a 64B/cycle link to the data fabric from the IO hub and then 32B/cycle link to each CCD. The single CCD packages will not get an extra data fabric link so as to keep it even between single and double CCD packages. So basically the double width facilitates double CCD packages with no cost to bandwidth. So that's how you get 16 cores on AM4 with two chiplets with plenty bandwidth. However the bandwidth should still be higher through better memory support but not double in that sense (depending on how you look at it). We'll see how it translates to real world performance in the reviews.

The IO part doesn't really worry me. 16+4+4x 4.0 PCIe lanes is ball park 48GB/s if you used it all at once. There's enough bandwidth to IF to cover that even at slow ram speeds. With fast ram (3000+), they could even get away without making that part wider. 

 

My concern remains the bandwidth between chiplets isn't a lot... comparable to accessing ram, which isn't a lot for so many cores. For maximum efficiency you'd probably want to keep workloads local to each chiplet and not cross that barrier if you can help it. Probably wont impact consumer workloads much, but at 12 and 16 cores we're entering new territories in the mainstream area.

[CarlBar]

8 hours ago, porina said:

I saw the efficiency bit but didn't see the "faster" bit. Charts seem to show same 32B/cycle as current for IF, which is still a bandwidth concern to me.

 

IF clock used to be half memory frequency. Now (using the default 1:1 ratio), it operates at memory frequency. So 3200Mhz by default. compared to the 1666MHz previously available thats a big uptick, more than double the cycles per second, and IF is bi directional whilst memory access is unidirectional. 

[porina]

1 hour ago, CarlBar said:

IF clock used to be half memory frequency. Now (using the default 1:1 ratio), it operates at memory frequency. So 3200Mhz by default. compared to the 1666MHz previously available thats a big uptick, more than double the cycles per second, and IF is bi directional whilst memory access is unidirectional. 

To my understanding IF was and still will be related to the true memory clock, which is half the marketing speed. That hasn't changed, other than now there's an even slower IF mode for those wishing to push ram faster.

 

It is unfortunate that AMD only chose to show how latency scaled with ram speed. It would be interesting to see bandwidth measurements also. 

[BiG StroOnZ]

AMD Ryzen 9 3950X (16-Core) Beats $2,000 Intel Core i9-9980XE (18-Core) In Geekbench Test:

Quote

 

 

A PC said to be using the yet to be released 16-core, 32-thread AMD Ryzen 9 3950X CPU appears to beat the 18-core, 36-thread Intel Core i9-9980XE in multi-core performance in a leaked Geekbench test result. Perhaps the craziest part about this is that Intel’s 18-core CPU sells for about $2,000, while AMD’s 3950X will be less than half of that at $750. The results show the AMD chip besting the Intel one in single-core score (5,868 vs. 5,395). But it's the 3950X's multi-core score (61,072) that's especially impressive, with a 31% advantage over the i9-9980XE, which scores (on average) only 46,618 points, according to Geekbench.

 

Granted, we don’t know the full story here and under which conditions the AMD CPU was tested. Geekbench shows the chip as having a 3.3 GHz base clock speed and a 4.3 GHz turbo clock speed, which may point to this chip being an engineering sample. That means that the Ryzen 9 3950X could show even better performance in the fall, as AMD advertised a 3.5-GHz base clock speed and a 4.7-GHz boosted clock speed for the chip. Current Geekbench results put the Intel Core i9- 9900K above the AMD 3950X in single-thread performance (6,209 vs. 5,868), but if the AMD chip truly ran at 4.3 GHz turbo clock speed in the test, then it could reach around 6,400 points in the fall at 4.7 GHz.

 

Source: https://www.tomshardware.com/news/amd-ryzen-3950x-vs-intel-i9-9980xe-geekbench,39640.html

 

Looking pretty good there Team Red! 

 

Still though, wait for independent reviews:

Also, something very interesting that was pointed out by Robert Hallock:

Quote

 

 

 

 

[Simon771]

On 6/11/2019 at 1:16 PM, leadeater said:

 

 

To Infinity and Beyond!

 

So the IF is still referenced to the memory clock but the ratio is adjustable.

 

 

Source: https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome (happy reading as there is WAY more information than I posted).

With previous generations IF speed was 1/2 of the RAM speed. So if I had 2933MHz RAM, IF speed was about half of that, so just under 1500.

If I understand that correctly, Zen2 will double the IF speed in the same scenario? So If I keep using 2933MHz ram, IF speed will also be 2933?

[Trixanity]

1 minute ago, Simon771 said:

With previous generations IF speed was 1/2 of the RAM speed. So if I had 2933MHz RAM, IF speed was about half of that, so just under 1500.

If I understand that correctly, Zen2 will double the IF speed in the same scenario? So If I keep using 2933MHz ram, IF speed will also be 2933?

99% sure it's the same as I assume it follows the principle of the actual RAM frequency. The example you give at 2933 MHz is the advertised speed due to it being DDR or Double Data Rate.

[leadeater]

45 minutes ago, Trixanity said:

99% sure it's the same as I assume it follows the principle of the actual RAM frequency. The example you give at 2933 MHz is the advertised speed due to it being DDR or Double Data Rate.

Think that is correct, the IF bus got wider. When they come out we'll actually know so waiting game really.

[Simon771]

7 hours ago, Trixanity said:

99% sure it's the same as I assume it follows the principle of the actual RAM frequency. The example you give at 2933 MHz is the advertised speed due to it being DDR or Double Data Rate.

 

6 hours ago, leadeater said:

Think that is correct, the IF bus got wider. When they come out we'll actually know so waiting game really.

I was reading this article about Infinity Fabric: https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/11

Guess I misunderstood those speeds ... could it be because I was hoping for 2x faster link between CCX chips, that could potentially lead to better performance in BDO, without having to disable some cores/threads. Then again we are less than a month away from release date, when all information will be available to us