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Another Complication In Processor Design :(

FirstArmada

With such problems arising on 14nm I wonder if this is the end of exponential growth, makes you wonder how low yields were in IBM's 7nm and 5nm node chips

 

For anyone wondering the basics of how this works:

 

Spoiler

1. Spin-coat the wafer with a uniform layer of photoresist fluid (roughly the consistency of thin maple syrup).


2. Expose the coated wafer to a bright light shown through a (very expensive) photoresist mask. Where the light reaches the photoresist fluid, it hardens. Areas which are not exposed remain liquid.


3. Rinse the coated wafer. This removes the unhardened photoresist fluid. The remaining hardened photoresist serves to protect ("mask") the underlying wafer.


4. Process the masked wafer using one of the following processes: wet acid etch, energized plasma etch, ion implantation, or metal deposition.


5. Remove the photoresist mask using a bake process ("ashing").


6. Clean the wafer (de-ionized water is frequently used)


7. Return to step 1.

 

Credit to: MailDeadDrop

Spoiler

 

Extreme UV chip defects may force a new approach to processor design

EUV has been the next big thing in chip manufacturing for nearly 30 years.

 

Chips built with extreme ultraviolet (EUV) light are plagued with random defects with no obvious solution, according to research presented at a chipmakers' conference reported in EETimes. The EUV hardware seems to work acceptably for 20nm or larger processes, but below this scale, small defects are cropping up that ruin the chip and prove hard to detect.

 

Photolithography is the process used to etch the patterns that make up chips into a silicon wafer. The wafer is coated with a light-sensitive material called photoresist. This wafer is then exposed to bright light that's shone through a mask. Areas hidden by the mask will retain their photoresist layer; those exposed directly to the UV will lose it. The wafer is then etched using plasma or acid. Parts of the wafer that are still covered in photoresist are protected during the etching, retaining their silicon oxide; those whose photoresist has been removed are etched away.

 

Smaller wavelengths of light enable finer detail in the mask and hence finer detail in the etching. Processors today, built on a 14nm process, already use features that are far smaller than the wavelength of regular UV light; they apply techniques such as multi-patterning (in which multiple masks and light exposure stages are used) to reach ever smaller sizes. These additional steps increase manufacturing time and error rates, hence the interest in shorter wavelengths. With EUV, smaller chip features could be produced without needing such techniques.

 

The chip-building industry has been talking about using EUV photolithography—light with a wavelength of 13.5nm, compared to the 193nm ultraviolet in use today—since the late 1990s. In theory, EUV should make it easier to build processors with smaller features—narrower wires, tinier transistors—but getting EUV to work has proven problematic. EUV is strongly absorbed by air and by the materials used to make lenses; it can still be focused and redirected, through the use of mirrors rather than lenses. Efficient generation of high-intensity EUV has also been difficult. Commercial applications need at least 250W light sources, with Intel claiming it needs as much as 1kW.

GlobalFoundries, Samsung, and TSMC have all outlined plans to use 250W EUV sources for 7nm manufacturing. This is at the level that researchers are seeing problems. These problems include both areas where not enough material is etched away, causing shorts between wires in the chip, and areas where too much is etched away, causing gaps and tears in things that should be continuous.

 

GlobalFoundries VP of Research George Gomba described similar defect problems with EUV and said that the EUV hardware—the NXE-3400 from ASML—wasn't yet up to the standard the company needs. He also said that better systems for inspecting the EUV masks are needed. Research is also needed to improve the photoresists, to understand their behavior when exposed to EUV and reduce the number of defects.

 

If these problems can't be ironed out, they may force a different approach to chip design. Chips that combine memory with processing elements and chips based on neural networks are more resilient to manufacturing defects, as the individual bad elements can be disabled while still salvaging the chip as a whole. IBM's True North neuron-simulating processor has a grid of 4096 elements, each combining some memory with some compute power, and last week researchers published that they had built "memtransistors." These combine transistors with memristors(devices that change their resistance depending on their "memory" of how much electric charge has passed through them). These hybrids integrate computation and memory at a very low level.

 

 

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These don't exist for the hell of it OP:

 

pls fix

 

Our Grace. The Feathered One. He shows us the way. His bob is majestic and shows us the path. Follow unto his guidance and His example. He knows the one true path. Our Saviour. Our Grace. Our Father Birb has taught us with His humble heart and gentle wing the way of the bob. Let us show Him our reverence and follow in His example. The True Path of the Feathered One. ~ Dimboble-dubabob III

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1 minute ago, DildorTheDecent said:

These don't exist for the hell of it OP:

 

pls fix

 

Am in the process of writing it up

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1 minute ago, FirstArmada said:

Am in the process of writing it up

Then just submit the written up version??? Instead of this copypasta mess.

 

Mods will merge if it already exists.

Our Grace. The Feathered One. He shows us the way. His bob is majestic and shows us the path. Follow unto his guidance and His example. He knows the one true path. Our Saviour. Our Grace. Our Father Birb has taught us with His humble heart and gentle wing the way of the bob. Let us show Him our reverence and follow in His example. The True Path of the Feathered One. ~ Dimboble-dubabob III

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3 minutes ago, DildorTheDecent said:

Mods will merge if it already exists.

But in that case, he wouldn't be the OP of the thread tho... :P (not like anyone actually cares...maybe...)

Looking at my signature are we now? Well too bad there's nothing here...

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

What? As I said, there seriously is nothing here :) 

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Centered OP's are painfull.

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EUV - Absorbed by everything including air, glass and the components of the EUV laser! More delays and issues than Intel's 10nm program!

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This could be a huge pain in the ass for the Fabs. Though if it persists, it might force interesting innovation in directions we haven't considered.

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Here to sympathize with OP. Sorry people get overly dramatic about formatting on this thread. One thing I find worse then bad formatting. Only one member needs to state it then the mods can take appropriate action if he doesn't correct.

 

Yes though you should follow the guidelines as they are there for the reason. Thanks for updating the news :) Peace.

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Any reports from AMD? They don't seem to be having as many delays as Intel and Nvidia on shrinking sizes. Maybe it's from such long projected timeline they gave room for delays

ƆԀ S₱▓Ɇ▓cs: i7 6ʇɥפᴉƎ00K (4.4ghz), Asus DeLuxe X99A II, GT҉X҉1҉0҉8҉0 Zotac Amp ExTrꍟꎭe),Si6F4Gb D???????r PlatinUm, EVGA G2 Sǝʌǝᘉ5ᙣᙍᖇᓎᙎᗅᖶt, Phanteks Enthoo Primo, 3TB WD Black, 500gb 850 Evo, H100iGeeTeeX, Windows 10, K70 R̸̢̡̭͍͕̱̭̟̩̀̀̃́̃͒̈́̈́͑̑́̆͘͜ͅG̶̦̬͊́B̸͈̝̖͗̈́, G502, HyperX Cloud 2s, Asus MX34. פN∩SW∀S 960 EVO

Just keeping this here as a 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7 hours ago, DildorTheDecent said:

These don't exist for the hell of it OP:

 

pls fix

 

 

Neither do these:

 

If there is a problem with a thread, use the report button to alert the mod team. Taking it upon yourself to tell the OP what to do is considered backseat moderation. At the very least if you're going to do it (which we'd prefer you not to), at least try not to be a dick about it. ;)

"Be excellent to each other" - Bill and Ted
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1 minute ago, Whiskers said:

Taking it upon yourself to tell the OP what to do is considered backseat moderation. At the *very* least if you're going to do it (which we'd prefer you not to), at least try not to be a dick about it. ;)

>Telling OP that he/she/it should have a wee read of the rules is wrong.

 

Are you high?

Our Grace. The Feathered One. He shows us the way. His bob is majestic and shows us the path. Follow unto his guidance and His example. He knows the one true path. Our Saviour. Our Grace. Our Father Birb has taught us with His humble heart and gentle wing the way of the bob. Let us show Him our reverence and follow in His example. The True Path of the Feathered One. ~ Dimboble-dubabob III

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1 minute ago, DildorTheDecent said:

>Telling OP that he/she/it should have a wee read of the rules is wrong.

 

Are you high?

 

If you disagree with our policy on this feel free to send me a PM to discuss it, but let's not derail OP's thread.

"Be excellent to each other" - Bill and Ted
Community Standards | Guides & Tutorials | Members of Staff

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22 hours ago, NMS said:

Oh god... Could you please remove the center alignment?

 

21 hours ago, CTR640 said:

Centered OP's are painfull.

 

Click source, and read original article if you don't like it.

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15 hours ago, BuckGup said:

Any reports from AMD? They don't seem to be having as many delays as Intel and Nvidia on shrinking sizes. Maybe it's from such long projected timeline they gave room for delays

Haven't read any reports about Global Foundries have seen report about TSMC, Samsung and Intel however.

 

It is possible they've spent more resources and time getting die size down as they saved a bunch of money by keep die variations to a minimum, for those who don't know Zen is composed of individual modules (i.e., dies) called Zeppelins that can be interconnected in a multi-chip module to form larger systems. The Threadripper die is the same as the Ryzen die. Likewise the EPYC family uses the same die. The differences between the processors is how those dies are connected together and which features are enabled and exposed.

 

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4 minutes ago, FirstArmada said:

Haven't read any reports about Global Foundries have seen report about TSMC, Samsung and Intel however.

Seems like Global Foundries anymore just contracts Samsung technology so if Samsung is having delays Global Foundries could very well and most likely be having them also.

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6 minutes ago, jman629 said:

Seems like Global Foundries anymore just contracts Samsung technology so if Samsung is having delays Global Foundries could very well and most likely be having them also.

They only licensed the 14nm process. Their 7nm is IBM. They bought all of IBM's foundry business. So they got former IBM staff mixed with existing talent working on 7nm and EUV. The guy in charge is former IBM too. They also continue to collaborate with IBM on research.

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29 minutes ago, Trixanity said:

They only licensed the 14nm process. Their 7nm is IBM. They bought all of IBM's foundry business. So they got former IBM staff mixed with existing talent working on 7nm and EUV. The guy in charge is former IBM too. They also continue to collaborate with IBM on research.

So the 7nm and 5nm chips IBM created were technically Global Foundries? 

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16 hours ago, Whiskers said:

 

 

If there is a problem with a thread, use the report button to alert the mod team. Taking it upon yourself to tell the OP what to do is considered backseat moderation. At the very least if you're going to do it (which we'd prefer you not to), at least try not to be a dick about it. ;)

THANK YOU! So sick of this backseat moderation.

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44 minutes ago, FirstArmada said:

So the 7nm and 5nm chips IBM created were technically Global Foundries? 

It's a collaboration. IBM still does research but they probably sold part of their business to reduce liability. Given the thread, it's evident that it's expensive and risky to spearhead silicon fabrication. 15 years ago there were like 25 companies. Today there are only 4.

GloFo today is in many ways an independent but extended arm of AMD and IBM. Those two are the primary customers and partners of GloFo. Neither wanted to continue in the same fashion Intel has and even Intel has realized it isn't sustainable to fab exclusively in-house.

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Sounds like its time to move up to vacuum chambers, UV lasers, and multi-head etching. imagine a grid of a dozen or more tiny UV lasers in a vacuum chamber over a silicon wafer, light and plasma being manipulated by the tiniest fractions of a nanometer via super strong magnets, and masks (if needed) that are arced, deep, and channeled like those sculptures that are thin planes of metal that can only be seen, and seen thru, from a specific angle

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