AMD Clarifies Why Threadripper Uses 4 Silicon Dies

[Lord Nicoll]

29 minutes ago, DXMember said:

someone did the math and it came to $1.80 for soldering all four dies on Threadripper, blank silicon dies with no transistors if probly cheap AF as well, the it's etching on the wafers that cost a lot (and only because of the R&D investment, when the factory is set up and running full production mode the expenses are minimal), no the wafers themselves

Vapour deposition isn't that cheap, but while it can be done en mass, those silicon bulbs that the disks are cut from cost millions, due to the required purity, however a single cylinder will make thousands of IC's, on it's own each is not that expensive, however I'd love to see the maths for myself. 

[Lord Nicoll]

1 hour ago, DocSwag said:

They had no transistors, who said they even need the wafers?

Amd said no transistors

The dies are cut from the water, the wafer is just each die all on a disk.

[Tam3n]

I'd guess they test the dies before soldering them on the chip. Then use the worst ones for spacers. Though it might be possible that the silicon ingot got areas that cannot be otherwise used, and they just cut dead pieces of silicon out of those.

[handymanshandle]

3 hours ago, Swatson said:

They did make a smaller socket, it's called AM4. They know they are going to have Threadripper parts at up to 32 cores just like Epyc. Epyc is on a "different" socket because it has to support dual socket features and more. Intel just likes to hyper fragment their market by having 4382948239 sockets.

 

As an aside:
The whole "Epyc is glued together desktop dies" is basically true, just as it is for Threadripper. The full 8 core, 2 CCX die is called Zeppelin, and Epyc /Threadripper are using 4 zeppelin dies while Ryzen (3, 5, and 7) uses 1 Zeppelin. This allows AMD to serve every market segment by producing one die and binning them, then using Infinity Fabric to connect them, it's pretty ingenious imo.

The thing is it's also true for most Xeon's (replace "dies" with "cores"). Intel just enables/disables some features/tweaks based on how much you're paying. They dont seem glued together because it's one big die but it's still just a bunch of the same cores you can find in a consumer product, they just "glue" them together at the die level using ringbus. Their 18 core planned i9 is just a cut down Xeon 22 core die IIRC.

It's like they're tailoring a sheet or a blanket of some sort out of silicon, and binding that silicon is thread or fabric of the infinity kind. Enchanting.

[Morgan MLGman]

2 hours ago, zMeul said:

to be translated: TSMC's process is so shit and unreliable that AMD can't produce big dies and have to use dead dies to offset the IHS balance

1. GloFo, 2. It's designed for scalability which Intel's current CPU design lacks.

[S w a t s o n]

An interesting consequence of AMD's choice to go MCM is that they can bin each zeppelin die to OC up to 4.0ghz. That means 4ghz 32 core threadripper/epyc chips are possible and probable eventually. They are limited by tdp/power right now probably.

 

Intel's method cannot do that (as easily) as they would have to bin entire 32 core dies at once. The 24 core Xeon they just released only has a base clock of 2.2ghz for example.

[Jito463]

4 hours ago, Swatson said:

As an aside:
The whole "Epyc is glued together desktop dies" is basically true, just as it is for Threadripper.

Just noticed this comment, and wanted to make a minor point of clarification: it's more accurate to say that Ryzen (and even TR) is a scaled down server die.  The Zen core was designed from the beginning to compete in the server market again, they just rolled out the desktop version first.  Which makes sense, as it doesn't require as much testing or certification as the server versions do.  It also has the side effect of allowing them to catch any bugs/errata that slipped through, and deal with them before they're introduced into the server lineup.

[S w a t s o n]

55 minutes ago, Jito463 said:

Just noticed this comment, and wanted to make a minor point of clarification: it's more accurate to say that Ryzen (and even TR) is a scaled down server die.  The Zen core was designed from the beginning to compete in the server market again, they just rolled out the desktop version first.  Which makes sense, as it doesn't require as much testing or certification as the server versions do.  It also has the side effect of allowing them to catch any bugs/errata that slipped through, and deal with them before they're introduced into the server lineup.

I'm not sure I would say scaled down. The die used in all Zen arch cpus is 8 core, 2CCX Zeppelin, epyc just had some additional features turned on if I understand correctly. I believe that Ryzen 7 should be able to support all features found in epyc except dual socket and 8 memory channels as those make use of the extra die's bandwidth/memory controller. In fact it's really about sticking CCXs together, AMD just chose to make dies with 2 of them, they could make a 32 core chip with 8 single CCX dies if they existed. However, it isn't right to call them desktop dies, that you are correct about.

In Intel's case I would say scaled down accurately describes it. 

[leadeater]

3 hours ago, Jito463 said:

I'm not even sure if it's possible for them to use a die without the memory controller, but I suppose we'll just have to wait and see.

 

By the by, I've been meaning to say for a while now, your avatar gif is really, really creepy and disturbing (which I'm fairly sure is what you were going for, but just so you knew).

 

3 hours ago, Swatson said:

They can choose to disable the memory controller, I'm almost certain. and thanks!

Memory channels can be there but they don't have to actually be used, you can run dual channel in a quad channel CPU/Motherboard. Memory channels is a possibility more than a requirement, you just should populate them fully for maximum bandwidth.

 

The other problem with Zen is if there isn't any memory attached to the IMC on the die everything for that die must go across the IF which would be a bit shit.

[leadeater]

1 hour ago, Swatson said:

I'm not sure I would say scaled down. The die used in all Zen arch cpus is 8 core, 2CCX Zeppelin, epyc just had some additional features turned on if I understand correctly. I believe that Ryzen 7 should be able to support all features found in epyc except dual socket and 8 memory channels as those make use of the extra die's bandwidth/memory controller. In fact it's really about sticking CCXs together, AMD just chose to make dies with 2 of them, they could make a 32 core chip with 8 single CCX dies if they existed. However, it isn't right to call them desktop dies, that you are correct about.

In Intel's case I would say scaled down accurately describes it. 

Every Zeppelin cluster across the entire range use the same dies, they all have the same features like ECC support etc. AMD then takes 1, 2 or 4 of these and puts them on a package to create the different products stacks.

 

The fact that TR and EPYC have more memory channels is solely from the use of more Zeppelin clusters, the only hardware difference in all of this is EYPC which has a separate but on package encryption chip no found on TR or Ryzen.

[S w a t s o n]

1 minute ago, leadeater said:

Every Zeppelin cluster across the entire range use the same dies, they all have the same features like ECC support etc. AMD then takes 1, 2 or 4 of these and puts them on a package to create the different products stacks.

 

The fact that TR and EPYC have more memory channels is solely from the use of more Zeppelin clusters, the only hardware difference in all of this is EYPC when has a seperate but on package encryption chip no found on TR or Ryzen.

Why does everyone agree with me but say it as if they don't Minus the encryption chip

[leadeater]

1 minute ago, Swatson said:

Why does everyone agree with me but say it as if they don't Minus the encryption chip

Well more of a clarification while agreeing since CPU feature wise there is no difference at all between the product stack and nothing is scaled up or down for any of them. If you're designing a scalable architecture then you are just implementing it to the scale you desire for the product.

 

Saying Ryzen is a scaled down EYPC is only slightly more correct since it has the same IMC and ECC support from that, without ECC official support stamped on the product.

 

Also to be fair I just forgot to quote @Jito463 as well.

1 hour ago, Swatson said:

8 memory channels as those make use of the extra die's bandwidth/memory controller.

Plus I didn't quite read that sentence correctly so... durp. Read it more like it has 8 channels but missed the why.

[Doobeedoo]

When it was revealed that it contains 4 it kinda made sense since they don't use some other socket for Threadripper but like Epyc. So fake dies for structural integrity are reasonable, wouldn't waste working dies. 

[Daniel644]

8 hours ago, Lord Nicoll said:

Those dies cost money, the wafers they're cut from are not cheap, the indium soldering process is also expensive, indium only wets to gold, gold won't wet to silicon either, you have to vapour deposit I think it's vanadium oxide then titanium and then gold to get the indium to stick to the silicon die, and the IHS needs a gold plating, and indium isn't cheap either, that is a lot of expense for two dummy dies, I'm not totally convinced. 

thats what I don't get, if they are just "spacers" why bother soldering them, surely the soldering job on the 2 active dies and all the glue that holds the IHS in place is enough.

[ravenshrike]

Just now, Daniel644 said:

thats what I don't get, if they are just "spacers" why bother soldering them, surely the soldering job on the 2 active dies and all the glue that holds the IHS in place is enough.

Because it adds at most a dollar per chip and probably less to solder the dead dies and this way they have no need to re-tool those particular parts of the assembly line from EPYC.

[Guest]

I like the fore thought and the potential cost savings this may lead to, just seems silly/ineffective now. 

 

 

[KuJoe]

9 hours ago, DiaSin said:

Basically, they are just spacers, there for structural integrity and nothing else.

Linus said this a week or two ago.

[Mihle]

They are produced in the same machine as Epyc, rather than having its own machine. That makes it cheeper.

[The Benjamins]

8 minutes ago, Mihle said:

They are produced in the same machine as Epyc, rather than having its own machine. That makes it cheeper.

the tooling cost of a different production line for a low volume chip out weights the cost of silicon rectangles and solder process.

[Jito463]

4 hours ago, Swatson said:

I'm not sure I would say scaled down.

I meant scaled down as in the number of dies, not in features/performance (though there are still some feature differences between Epyc, TR and Ryzen).  Obviously the whole point of Zen is scalability (adding more dies as needed); but as I understand it, it was built first and foremost for the server, then "scaled down" to the desktop.  That was all I meant by that comment.

[Kukielka]

5 minutes ago, huilun02 said:

Right lets fixate on our negative opinions about how Ryzen/TR/Epyc is made, instead of the end result of great perf for the price. 

Yea, let's treat it the way Intel is treated. Sounds about right to me

[Princess Luna]

Well TR still looks way more interesting to me than the i9 line up.

[Mira Yurizaki]

11 hours ago, Lord Nicoll said:

Those dies cost money, the wafers they're cut from are not cheap, the indium soldering process is also expensive, indium only wets to gold, gold won't wet to silicon either, you have to vapour deposit I think it's vanadium oxide then titanium and then gold to get the indium to stick to the silicon die, and the IHS needs a gold plating, and indium isn't cheap either, that is a lot of expense for two dummy dies, I'm not totally convinced. 

Who said they were even from silicon wafers?

[The Benjamins]

9 minutes ago, M.Yurizaki said:

Who said they were even from silicon wafers?

also isn't the biggest cost to a wafer the printing of the transistors then the preparation of the wafer it self?

[2FA]

8 hours ago, DXMember said:

someone did the math and it came to $1.80 for soldering all four dies on Threadripper, blank silicon dies with no transistors if probly cheap AF as well, the it's etching on the wafers that cost a lot (and only because of the R&D investment, when the factory is set up and running full production mode the expenses are minimal), no the wafers themselves

You would be correct. A wafer only costs a few hundred dollars and you get 50+ dies per wafer. For actual etching, there are at least a half dozen machines that a wafer has to go through to produce functioning dies and each machine costs millions of dollars. 

 

Blank dies really only have to go through the first machine which creates the base structure of the die.