PCIe 4.0 *FINALLY* Finalized

[Sniperfox47]

Not sure how we got a post about the 5.0 announcement but somehow missed that the 4.0 spec is finalized after sitting in limbo for a long time.

 

http://techreport.com/news/32064/pcie-4-0-specification-finally-out-with-16-gt-s-on-tap

 

Quote

Although it started as a key I/O component in PCs, PCIe now serves as the interconnect for any number of devices, including those in the server, storage, and mobile markets. The full details of the new specification haven't yet been published on the consortium's website, but we're told that it doubles the per-pin bandwidth of the previous generation, offering 16 GT/s data rates.

 

While full details aren't yet available for the final spec, the details we do have so far are pretty juicy. Huge sweeping changes to the PHY layer should lead to better latency and much lower power use, so there's the possibility we could start to see this in high end ARM devices.

 

With 5.0 being officially announced at the same time, with a planned release in just two years it'll be interesting to see if AMD or Intel even bother to impliment this on the consumer side of things.

 

Quote

The PCIe 4.0 specification still needs to undergo a final IP review, but the PCI-SIG claims that the interconnect is ready to go. Prior to the publication of the spec, the SIG had already been doing compliance testing with a variety of its members, and it claims that a number of 16 GT/s solutions have already been worked out. Perhaps we'll see products using the new spec make their way to shelves sooner than later.

 

Products with it are on their way but keep in mind a lot of these are likely Enterprise products for high end servers where existing PCIe 3.0 interconnects are being fully loaded. I'd be really shocked if there's anything on the consumer side coming Immediately.

 

[kelvinhall05]

IMO the real question is when will we start seeing PCIe 4.0 capable devices?

[knightslugger]

2 minutes ago, Sniperfox47 said:

it'll be interesting to see if AMD or Intel even bother to impliment this on the consumer side of things.

what, pray tell, could even output that sort of bandwidth on consumer level devices at 16x 3.0, let alone 4.0...?

[Sniperfox47]

Just now, kelvinhall05 said:

IMO the real question is when will we start seeing PCIe 4.0 capable devices?

They're coming out imminently. Next few months. That being said they're not likely consumer level devices, more devices meant for high scale servers.

Just now, knightslugger said:

what, pray tell, could even output that sort of bandwidth on consumer level devices at 16x 3.0, let alone 4.0...?

The benefit on the consumer side is using less lanes for existing devices. For example high end SSDs with full speed out of 2 lanes instead of 4. 20 PCIe 4.0 lanes will be easier to implement than 40 PCIe 3.0 lanes.

[Sakkura]

Some chips were already taped out with PCIe 4.0 support based on the 0.7 revision of the spec. So the first enterprise products with PCIe 4.0 should not be far off.

 

Will take longer for the consumer market, obviously. And I'm worried about the limitations on trace length (or needing repeaters). Could make motherboards more expensive or limit adoption.

[knightslugger]

3 minutes ago, Sniperfox47 said:

The benefit on the consumer side is using less lanes for existing devices. For example high end SSDs with full speed out of 2 lanes instead of 4. 20 PCIe 4.0 lanes will be easier to implement than 40 PCIe 3.0 lanes.

we don't even use them all anyway!

[Sniperfox47]

1 minute ago, Sakkura said:

Some chips were already taped out with PCIe 4.0 support based on the 0.7 revision of the spec. So the first enterprise products with PCIe 4.0 should not be far off.

 

Will take longer for the consumer market, obviously. And I'm worried about the limitations on trace length (or needing repeaters). Could make motherboards more expensive or limit adoption.

I thought that's part of why they underwent such massive changes to the PHY tuning and tweaking things and it wound up delayed so long, specifically so they could take care of some of the signal issues?

[Sakkura]

Just now, Sniperfox47 said:

I thought that's part of why they underwent such massive changes to the PHY tuning and tweaking things and it wound up delayed so long, specifically so they could take care of some of the signal issues?

Sure, but trace lengths still can't be as long as PCIe 3.0.

[knightslugger]

1 minute ago, Sakkura said:

Sure, but trace lengths still can't be as long as PCIe 3.0.

moar powah!

[Sniperfox47]

4 minutes ago, Sakkura said:

Sure, but trace lengths still can't be as long as PCIe 3.0.

I'll keep living in my sci-fi fantasy where we get optical traces on the motherboard for PCIe so they can be pretty much as long as we want.

 

And before you say that would be even more expensive, I don't care xP optical traces would be cool.

[ARikozuM]

13 minutes ago, knightslugger said:

what, pray tell, could even output that sort of bandwidth on consumer level devices at 16x 3.0, let alone 4.0...?

Using less lanes would be an advantage if AMD and Intel can add support soon.

[Taf the Ghost]

26 minutes ago, kelvinhall05 said:

IMO the real question is when will we start seeing PCIe 4.0 capable devices?

Mid-2018 seems likely. One of the SSD makers has it on the roadmap for Q4`2018

[Sniperfox47]

4 minutes ago, Taf the Ghost said:

Mid-2018 seems likely. One of the SSD makers has it on the roadmap for Q4`2018

The PCIe SIG said in their announcement of 4 being finalized that they have a number of partners ready to release products already after a final review.

 

With what Sakkura mentioned above, about chips/controllers already being taped out, it's very probable these will see the light of day by end of 2017.

 

Again it's very probable these aren't consumer devices though.

[Taf the Ghost]

27 minutes ago, Sakkura said:

Some chips were already taped out with PCIe 4.0 support based on the 0.7 revision of the spec. So the first enterprise products with PCIe 4.0 should not be far off.

 

Will take longer for the consumer market, obviously. And I'm worried about the limitations on trace length (or needing repeaters). Could make motherboards more expensive or limit adoption.

Icelake or Tigerlake are the first chance we'll see them on the Consumer level.  I'd expect it for 2019 refreshes of X299 and X399, though, as it's much more use for the HEDT market over the Mainstream.  

[Sniperfox47]

Also of interest: does this mean OCuLink 2.0 is finalized as well? Wonder what the max length is on it and if we might see it on the consumer side this time around.

[Mira Yurizaki]

33 minutes ago, Sakkura said:

Will take longer for the consumer market, obviously. And I'm worried about the limitations on trace length (or needing repeaters). Could make motherboards more expensive or limit adoption.

However if we can convince video card manufacturers that they don't really need the x16 slot form factor anymore, then you can get away with running less traces over the motherboard.

[SpaceGhostC2C]

35 minutes ago, Sniperfox47 said:

20 PCIe 4.0 lanes will be easier to implement than 40 PCIe 3.0 lanes.

I hope so, but that's not how it played out from PCIe 2.0 to 3.0 in the consumer platform: all the consumer boards are like "if you use slot X, forget about slot Y", it barely makes sense having a full ATX motherboard, but older platforms limited to PCIe 2.0 would let you use 90% of the slots at the same time, worst case scenario a x16 slot turned to x8, and that's it.

So we may have higher total bandwidth, but certainly gave up some lanes in the process.

[Princess Luna]

Does it retain backwards compatibility and all?

[Sakkura]

9 minutes ago, M.Yurizaki said:

However if we can convince video card manufacturers that they don't really need the x16 slot form factor anymore, then you can get away with running less traces over the motherboard.

Yeah, as long as it doesn't get overridden by "big numbers marketing."

[Mira Yurizaki]

9 minutes ago, Princess Cadence said:

Does it retain backwards compatibility and all?

If it didn't, the PCI-SIG basically signed its own death warrant to any other competitors (like CCIX)

 

Okay, maybe it won't be that dramatic, but backwards and forwards compatibility is one of PCIe's biggest strengths.

[Sniperfox47]

9 minutes ago, Princess Cadence said:

Does it retain backwards compatibility and all?

Afaik it's fully backwards compatible since that was kind of the whole point of keeping it as a PCIe standard rather than switching to a new interconnect.

 

That being said, somebody on the PCIe 5.0 thread pointed out an article that said compatibility was one-way so maybe I'm wrong.

 

OCuLink 2 is not backwards compatible with OCuLink, but that never really made it to the consumer side anyways. OCuLink 2 is relatively future proof though.

[The Benjamins]

27 minutes ago, Princess Cadence said:

Does it retain backwards compatibility and all?

 

16 minutes ago, Sniperfox47 said:

Afaik it's fully backwards compatible since that was kind of the whole point of keeping it as a PCIe standard rather than switching to a new interconnect.

 

That being said, somebody on the PCIe 5.0 thread pointed out an article that said compatibility was one-way so maybe I'm wrong.

 

OCuLink 2 is not backwards compatible with OCuLink, but that never really made it to the consumer side anyways. OCuLink 2 is relatively future proof though.

Isn't PCIe backwards and forwards compatible.

Backwards is Gen 1 device in a Gen 2 socket

Forwards is Gen 2 device in a Gen 1 socket

examples USB is forwards and backwards compatible when AM3+ is only backwards.

[AnonymousGuy]

33 minutes ago, The Benjamins said:

 

Isn't PCIe backwards and forwards compatible.

Backwards is Gen 1 device in a Gen 2 socket

Forwards is Gen 2 device in a Gen 1 socket

examples USB is forwards and backwards compatible when AM3+ is only backwards.

Yes, pcie is one of few things that has full forwards and backwards compatibility.  You can even plug PCI 1.2? devices in to a PCIe slot with an adapter. 

[Juanitology]

2 hours ago, Sniperfox47 said:

They're coming out imminently. Next few months. That being said they're not likely consumer level devices, more devices meant for high scale servers.

The benefit on the consumer side is using less lanes for existing devices. For example high end SSDs with full speed out of 2 lanes instead of 4. 20 PCIe 4.0 lanes will be easier to implement than 40 PCIe 3.0 lanes.

Actually high-end SSDs are already close to hitting a wall with 3.5+GB/s sequential speeds. The 4x PCIe interface has a theoretical 4GB/s limit although in practice it's slightly less due to encoding overhead. Probably by this time next year we'll have an SSD that can saturate it.

[tlink]

4 hours ago, Sniperfox47 said:

I'll keep living in my sci-fi fantasy where we get optical traces on the motherboard for PCIe so they can be pretty much as long as we want.

 

And before you say that would be even more expensive, I don't care xP optical traces would be cool.

now make it rgb for extra data throughput and cool light effects.