AMD New Horizon

[Dabombinable]

1 minute ago, Drak3 said:

That's nice and fine, it doesn't change the fact that AMD made an octocore that had an architecture that went against every method developers used, and it suffered for it.

It doesn't change the fact that the only people claiming that AMD's modules are cores don't know what actually constitutes a core or how CMT is intended to work.

4 module, 8 core. Simple as that, and I'll post the SS so you can take a hint-if CMT consisted of actual cores, then why is a "4 core" A8 4555M as fast as a dual core i5 U470 which boosts to 1.6GHz? And around half the speed of a Phenom II X4?

 

If I can resurrect my laptop again, I should re-install the original Phenom II X4 P920 for direct comparison, it runs at 1.6GHz base as well.

[Drak3]

Just now, Dabombinable said:

4 module, 8 core. Simple as that, and I'll post the SS so you can take a hint-if CMT consisted of actual cores, then why is a "4 core" A8 4555M as fast as a dual core i5 U470 which boosts to 1.6GHz? And around half the speed of a Phenom II X4?

 

If I can resurrect my laptop again, I should re-install the original Phenom II X4 P920 for direct comparison, it runs at 1.6GHz base as well.

Because that quadcore has a pathetic IPC (Bulldozer, clock for clock, was worse performance than its predecessors), and Bulldozer can't feed instructions to all cores simultaneously, it's one, then the other. In workloads with short threads of instructions, not all cores are active with the task at hand.

CMT was intended for workloads with long threads of instruction, so that one core could be fed instructions while the other was still working.

[Dabombinable]

10 minutes ago, Drak3 said:

Because that quadcore has a pathetic IPC (Bulldozer, clock for clock, was worse performance than its predecessors), and Bulldozer can't feed instructions to all cores simultaneously, it's one, then the other. In workloads with short threads of instructions, not all cores are active with the task at hand.

CMT was intended for workloads with long threads of instruction, so that one core could be fed instructions while the other was still working.

Will you still say that after I do another run, and you see the multithreaded multiplier?

[leadeater]

8 minutes ago, Drak3 said:

Because that quadcore has a pathetic IPC (Bulldozer, clock for clock, was worse performance than its predecessors), and Bulldozer can't feed instructions to all cores simultaneously, it's one, then the other. In workloads with short threads of instructions, not all cores are active with the task at hand.

CMT was intended for workloads with long threads of instruction, so that one core could be fed instructions while the other was still working.

I guess a better argument would be it was a bad idea to design a CPU that requires a workload not often used in the light use consumer environments. I actually liked the design idea and was interested to see how it actually worked so I was a little disappointed in how it turned out. It may still be the case that the design could work very well and AMD just needed to completely redesign it from the ground up, but with such bad stigma and needing a 100% sure bet it was much safer to go with the accepted norm.

[Drak3]

1 minute ago, Dabombinable said:

Will you still say that after I do another run, and you see the multithreaded multiplier?

Yes, want to know why?

 

A single benchmark isn't reliable, especially one that doesn't take into account that CMT and SMT are different multithreading technologies.

Windows itself doesn't differentiate between CMT and SMT, because CMT was unprecedented, and it flopped because it wasn't a better alternative.

 

But it doesn't change that an FX 8320 is an 8 core, or an A10-6800K a quad core. It doesn't change the fact that Bulldozer has 2 cores per module.

[Dabombinable]

Just now, Drak3 said:

Yes, want to know why?

 

A single benchmark isn't reliable, especially one that doesn't take into account that CMT and SMT are different multithreading technologies.

Windows itself doesn't differentiate between CMT and SMT, because CMT was unprecedented, and it flopped because it wasn't a better alternative.

 

But it doesn't change that an FX 8320 is an 8 core, or an A10-6800K a quad core. It doesn't change the fact that Bulldozer has 2 cores per module.

Spoiler alert, you can't set the affinity of processes to each "core" and have them run as fast as they would set to 1 module, unlike with true multi core CPU, or SMP setups.

[Drak3]

2 minutes ago, Dabombinable said:

Spoiler alert, you can't set the affinity of processes to each "core" and have them run as fast as they would set to 1 module, unlike with true multi core CPU, or SMP setups.

It might have something to do with the fact that Windows doesn't recognize CMT as CMT, or that the bulldozer CPUs and APUs switch between cores to feed instruction based upon how load is being applied on a firmware level within a module, not a software level on an overall scale.

Here's a hint: If there isn't enough instruction to keep one core active while the other can be fed, CMT won't try to make both cores active. It results in underperforming CPUs when used in the wrong scenarios.

[Dabombinable]

45 minutes ago, Drak3 said:

It might have something to do with the fact that Windows doesn't recognize CMT as CMT, or that the bulldozer CPUs and APUs switch between cores to feed instruction based upon how load is being applied on a firmware level within a module, not a software level on an overall scale.

Here's a hint: If there isn't enough instruction to keep one core active while the other can be fed, CMT won't try to make both cores active. It results in underperforming CPUs when used in the wrong scenarios.

Windows still has had the neccesary patch to make it CMT compatible. And no matter how you try to deny otherwise, you can not allocate 1 program per thread and have them run as well as they do with a module to itself. And FYI, if for example my A8 4555M had 1 program allocated to each "core", it would have enough to keep the entire module active. Also, core parking can be disabled.....

[Drak3]

5 minutes ago, Dabombinable said:

Windows still has had the neccesary patch to make it CMT compatible. And no matter how you try to deny otherwise, you can not allocate 1 program per thread and have them run as well as they do with a module to itself. And FYI, if for example my A8 4555M had 1 program allocated to each "core", it would have enough to keep the entire module active. Also, core parking can be disabled.....

Being compatible and recognizing are two different issues. Windows does not need to recognize CMT to run on it, it just has to play nicely with the CPU's firmware.

CPU affinity is by no means a metric of measuring core count. If it was, it'd mean that my 5930K was a fucking dodecacore. Guess what my 5930K isn't.

If you were to try to allocate the typical program, or most benchmarks out there, to a single module on a Bulldozer CPU, the instruction threads wouldn't be long enough to keep both cores active.

Core parking in Windows doesn't change how the CPU operates, or how the firmware works. Unless the CPU is fed enough instruction to feed one core, switch to feed the other, and not have the first core finish and waiting for the second to be fed, CMT will not be used correctly by Windows, even if you disable core parking.

[That Norwegian Guy]

1 hour ago, Drak3 said:

The integer cluster and ALU are the only components that actually make a core. The FPU is a separate, yet vital component.

Very few of us give a crap about those kind of semantics, just a heads up. Over the past two to three decades consumers have come to expect an FPU with every core and so the reality of what a core is to a consumer has changed and so has the proper marketing language. With the amount of floating point math in applications today it's irrelevant whether or not an FPU technically is required to allow you to call your core a core, as long as you are being punished hard by consumers for omitting to include the proper amount of them.

[Drak3]

1 minute ago, That Norwegian Guy said:

Very few of us give a crap about those kind of semantics, just a heads up. Over the past two to three decades consumers have come to expect an FPU with every core and so the reality of what a core is to a consumer has changed and so has the proper marketing language. With the amount of floating point math in applications today it's irrelevant whether or not an FPU technically is required to allow you to call your core a core, as long as you are being punished hard by consumers for omitting to include the proper amount of them.

Few people care about the semantics, but even fewer are stupid enough to try to make an issue of something without knowing what the fuck is going on. It's the second group of people that need to know the semantics of what they're uttering, otherwise, it's just uneducated bullshit, and a waste of time for everyone involved.

Consumers aren't punishing AMD because they use CMT, or that the cores work within modules to achieve an end goal somewhat similar to SMT. They're punishing AMD for putting out CPUs that were, clock for clock, worse than their predecessors. They're punishing AMD for making marginal improvements on them for years at the low end, while the only competition they had were releasing medium end product better than AMD's high end.

[MageTank]

43 minutes ago, Drak3 said:

Few people care about the semantics, but even fewer are stupid enough to try to make an issue of something without knowing what the fuck is going on. It's the second group of people that need to know the semantics of what they're uttering, otherwise, it's just uneducated bullshit, and a waste of time for everyone involved.

Consumers aren't punishing AMD because they use CMT, or that the cores work within modules to achieve an end goal somewhat similar to SMT. They're punishing AMD for putting out CPUs that were, clock for clock, worse than their predecessors. They're punishing AMD for making marginal improvements on them for years at the low end, while the only competition they had were releasing medium end product better than AMD's high end.

I thought they were punishing AMD for taking a step backwards, clock for clock, from Phenom II, then "improving it" by selling the same CPU several times, with different factory overclocks (FX8320, FX8350, FX9590). No matter how it plays out, CMT, while great in theory, failed. AMD knows this, and it's why they opted for a different design this time around. Trying to justify what didn't work seems silly at this point, but I suppose I see your point. You are trying to convey the message that the FX8 series had 8 cores, combating against the current notion that they only have 4 modules.

 

An easier way to win your fight, is to simply change the analogy at hand. If AMD cannot advertise the FX8 series as Octocore processors, then every mobo manufacturer (from both Intel and AMD) should not be allowed to advertise 10+phase VRM's when they use doublers or triplers. At the end of the day, you still have the phases, just like you still have 8 threads on the FX8 series. Just a lackluster implementation of them, lol. 

[Drak3]

7 minutes ago, MageTank said:

I thought they were punishing AMD for taking a step backwards, clock for clock, from Phenom II

 

59 minutes ago, Drak3 said:

They're punishing AMD for putting out CPUs that were, clock for clock, worse than their predecessors.

Uh....

Those two statements seem very similar. Almost like they communicate the same point, just worded differently.

9 minutes ago, MageTank said:

then "improving it" by selling the same CPU several times, with different factory overclocks (FX8320, FX8350, FX9590)

I was talking about Carrizo, the best (in terms of IPC) the Bulldozer architectures had to offer. They don't have the highest clocks, but they are a little better than their older brethren and sistren.

 

 

And the issue isn't the question of threads an FX8 processor has. It's that it runs on a 4 module, 8 core implementation that was expected to act exactly like any other octocore.

[MageTank]

1 minute ago, Drak3 said:

 

Uh....

Those two statements seem very similar. Almost like they communicate the same point, just worded differently.

I was talking about Carrizo, the best (in terms of IPC) the Bulldozer architectures had to offer. They don't have the highest clocks, but they are a little better than their older brethren and sistren.

 

 

And the issue isn't the question of threads an FX8 processor has. It's that it runs on a 4 module, 8 core implementation that was expected to act exactly like any other octocore.

Woah, I can't believe I read "predecessors" as "processors". In my head, when you said:

Quote

Consumers aren't punishing AMD because they use CMT, or that the cores work within modules to achieve an end goal somewhat similar to SMT. They're punishing AMD for putting out CPUs that were, clock for clock, worse than their predecessors.

I interpreted it as "their processors" being AMD's CMT vs Intel's SMT (Hyperthreading). I suppose it's time for bed, lol.

[Drak3]

1 minute ago, MageTank said:

Woah, I can't believe I read "predecessors" as "processors". In my head, when you said:

I interpreted it as "their processors" being AMD's CMT vs Intel's SMT (Hyperthreading). I suppose it's time for bed, lol.

Well, AMD's first implementation of CMT is worse than Hyperthreading, and it's WAY worse than POWER8's 8 way SMT.

[done12many2]

Well guys and gals, here's the official answer.  It was definitely the render sample casing the disparity between AMD's results and the public's.  They were using 150 while the file that they made available for your own comparison defaulted to 200.

 

AMD will be uploading a new Blender file with the sample set correctly at 150.  That will definitely result in a much more believable outcome when you are trying to compare your setup with that of the AMD New Horizon comparison tests.

 

 

[Citadelen]

AMD James informed us how to do the Blender run properly. 

Set render samples to 150, a new file will be uploaded shortly, and they apologise for the confusion. Blender 2.78a x64 was used.

[porina]

8 hours ago, MageTank said:

Anyone that has ran blender, should look at those times and automatically question their validity. I don't even own an 8 core SKU, and I question it, lol. 

AMD want to give the impression that Ryzen 3.4 GHz = 6900k stock, and will probably undercut it by some not insignificant amount on launch and trumpet that. Of course, the full statement should include the phrase "in this Blender test." This then swings around to another question, how does the AMD Blender test actually behave? I tried to answer that with limited testing. I put a longer post in another thread but the summary would be:

 

• Ram speed doesn't seem to make a significant difference (<1%, 6700k 4.2 GHz, 2666 vs 2133 dual channel dual rank. I didn't try crippling the ram further)
• 6MB to 8MB L3 cache doesn't seem to make a difference (<1%, 6600k vs 6700k HT off)
• HT gives a significant boost, about 52% faster (or, takes 66% of the time compared to HT off)
• Haswell to Broadwell, and Broadwell to Haswell gave about 3% IPC boost each. Caution limited test samples, I'll see if I can use the other linked sheet to verify this.
• Pentium G4400 IPC 4% lower than 6600k. The G4400 is Skylake without AVX extensions, suggesting those are not used as I'd expect a much bigger difference if it was.

So although this Blender test does use all available threads, it doesn't seem to be a particularly heavy stress.

[XenosTech]

 - 150 samples

- 100 samples

 

meh

[MrDynamicMan]

On 14/12/2016 at 1:08 AM, lilbman said:

lol don't we all?

You must've forgotten @zMeul

[Prysin]

49 minutes ago, porina said:

AMD want to give the impression that Ryzen 3.4 GHz = 6900k stock, and will probably undercut it by some not insignificant amount on launch and trumpet that. Of course, the full statement should include the phrase "in this Blender test." This then swings around to another question, how does the AMD Blender test actually behave? I tried to answer that with limited testing. I put a longer post in another thread but the summary would be:

 

• Ram speed doesn't seem to make a significant difference (<1%, 6700k 4.2 GHz, 2666 vs 2133 dual channel dual rank. I didn't try crippling the ram further)
• 6MB to 8MB L3 cache doesn't seem to make a difference (<1%, 6600k vs 6700k HT off)
• HT gives a significant boost, about 52% faster (or, takes 66% of the time compared to HT off)
• Haswell to Broadwell, and Broadwell to Haswell gave about 3% IPC boost each. Caution limited test samples, I'll see if I can use the other linked sheet to verify this.
• Pentium G4400 IPC 4% lower than 6600k. The G4400 is Skylake without AVX extensions, suggesting those are not used as I'd expect a much bigger difference if it was.

So although this Blender test does use all available threads, it doesn't seem to be a particularly heavy stress.

well, it doesnt seem like the model of the Ryzen logo is that complex, so that is probably why it is so easy to run. Still aslong as things are "equally" easy between both manufacturers, then things are "fair".

 

Have you checked to see if the blender test offloads any workload to any form of fixed function hardware?

[XenosTech]

2 minutes ago, MrDynamicMan said:

You must've forgotten @zMeul

aka mr lick steam hardware survey's ass

[zMeul]

@MrDynamicMan @XenosTech

I've stayed out of this discussion, want me to blow it up? I'll do it 

[Astronautical]

Why did they crop the intel screen so you cant see the programs running dure in the benchmark? Not to be against amd but thats suspicious to me.

[Space Reptile]

1 hour ago, XenosTech said:

 - 150 samples

- 100 samples

meh

and people say sandy sucks lol , beat you by 6 seconds  

 

(even in passmark oddly enough , granted I have more threads but single core reading is only 1% better on the 6500 ....)