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Ryzen Threadripper Delidding

4 minutes ago, H0R53 said:

Who cares? We all know it's just 4 dies glued together

Just remember trolling is against the Community Standards ;).

 

Care to expand on why 4 dies connected by a fabric is a problem? You're thoughts on it? Evidence you have to come to your reasoning? Anything to actually add at all?

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3 minutes ago, leadeater said:

Just remember trolling is against the Community Standards ;).

 

Care to expand on why 4 dies connected by a fabric is a problem? You're thoughts on it? Evidence you have to come to your reasoning? Anything to actually add at all?

How does making a joke equate to trolling?

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6 minutes ago, H0R53 said:

How does making a joke equate to trolling?

That's not a discussion I'm going to have in thread, and as I said it's only reminder. Any posts intended to cause arguments or generally derail the thread is a problem, I also make judgments on past comments including ones that have been hidden by moderation staff.

 

Too many threads recently have gotten in to multiple page arguments, gone way off topic and have been generally disruptive to the community which we get complains about.

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Just now, leadeater said:

That's not a discussion I'm going to have in thread, and as I said it's only reminder. Any posts intended to cause arguments or generally derail the thread is a problem, I also make judgments on past comments including ones that have been hidden by moderation staff.

 

Too many threads recently have gotten in to multiple page arguments, gone way off topic and have been generally disruptive to the community which we get complains about.

Oh, like the thread that was titled "Intel q2 earnings rip AMD a new asshole"

 

Yeah, sorry bout that one

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14 hours ago, mariushm said:

The socket doesn't have extra pins for 32 pci-e lanes. AM4+ would need to have more pins so it would not be backwards compatible.  No, i think we're pretty much stuck on 24 pci-e lanes.

I figured as much, thanks for clarifying it though.

14 hours ago, mariushm said:

TR is max 2 dies, so max 16 core/32 threads and 2 x 2 channel, max 8 ddr4 sticks and 128? GB of memory. Don't think socket supports more ddr channels (no pins

I suppose they could make dies in future with more than 2 ccx but i doubt it.

If anything they'll probably add a 10/20 core threadripper in a few months - right now they'd want to push people into buying 12/16 core models and not steal sales from either higher end or the lower 8core ryzen and the dies are probably just too good to kill 3 cores from each die to make a 10 core TR now.

I thought that the Ryzen platform had to disable cores evenly between the CCXs.

2/2 for 4 core.

3/3 for 6 core.

4/4 for 8 core.

3/3/3/3 for 12 core.

4/4/4/4 for 16 core.

If I am correct, than a 10 core Threadripper would not be possible.  Please correct me if I am wrong though.

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6 hours ago, Doobeedoo said:

I'm to surprised really, seeing the socket used, not making new one to save price and all. And dies are not wasted, but rather fake dies to offer structural integrity for IHS so yeah.

I think it may have actually saved them money to go with a similar socket/substrate size, as it would allow them to simply re-use the same manufacturing methodology. I see the "dummy dies" serving the purpose of improving rigidity on the substrate (especially under extreme mounting pressure) while once again allowing them to use previous manufacturing methods to build the CPU's.

 

The more I think about it, using only 2 dies for threadripper, while keeping socket and substrate size the same, would have been pretty silly, especially if you wanted pressure across the IHS to be even so that you don't randomly crush dies. I know the socket retention mechanism is designed to absorb most of that pressure, but it seems AMD spared no expense this time around to at least make sure the product itself was physically solid. You wouldn't be able to emulate it quite perfectly with just using silicone adhesive in those area's either, as it might result in uneven mounting on the dies themselves in regards to the IHS.

 

All around, this was probably their best move. If these are not "dummy dies" and are actually real, then I fully expect classic AMD shenanigans to ensue. Turning 720 Heka's into quad core denebs, except on a much more extreme scale, lol. 

My (incomplete) memory overclocking guide: 

 

Does memory speed impact gaming performance? Click here to find out!

On 1/2/2017 at 9:32 PM, MageTank said:

Sometimes, we all need a little inspiration.

 

 

 

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8 minutes ago, MageTank said:

I think it may have actually saved them money to go with a similar socket/substrate size, as it would allow them to simply re-use the same manufacturing methodology. I see the "dummy dies" serving the purpose of improving rigidity on the substrate (especially under extreme mounting pressure) while once again allowing them to use previous manufacturing methods to build the CPU's.

 

The more I think about it, using only 2 dies for threadripper, while keeping socket and substrate size the same, would have been pretty silly, especially if you wanted pressure across the IHS to be even so that you don't randomly crush dies. I know the socket retention mechanism is designed to absorb most of that pressure, but it seems AMD spared no expense this time around to at least make sure the product itself was physically solid. You wouldn't be able to emulate it quite perfectly with just using silicone adhesive in those area's either, as it might result in uneven mounting on the dies themselves in regards to the IHS.

 

All around, this was probably their best move. If these are not "dummy dies" and are actually real, then I fully expect classic AMD shenanigans to ensue. Turning 720 Heka's into quad core denebs, except on a much more extreme scale, lol. 

Yeah exactly.
What I meant with bold corrected.

 

7 hours ago, Doobeedoo said:

I'm not to surprised really, seeing the socket used, not making new one to save price and all. And dies are not wasted, but rather fake dies to offer structural integrity for IHS so yeah.

 

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9 hours ago, Cinnabar Sonar said:

I figured as much, thanks for clarifying it though.

I thought that the Ryzen platform had to disable cores evenly between the CCXs.

2/2 for 4 core.

3/3 for 6 core.

4/4 for 8 core.

3/3/3/3 for 12 core.

4/4/4/4 for 16 core.

If I am correct, than a 10 core Threadripper would not be possible.  Please correct me if I am wrong though.

They don't HAVE to, they do it for consistency.

 

All threads on one CCX are the same performance, but there is very small some performance loss when two threads each on another CCX have to exchange data between them.

AMD cuts cores from each CCX as even as possible, so that software developers and compilers won't be "motivated" to write hacks or tricks that would give threads from one CCX more importance than the other threads.

 

For example, let's say you have an application that uses exactly 4 threads to do stuff.

With quad core processors (leaving aside issues of uneven temperature and power usage) AMD could have cut the four cores from one CCX leaving the processor with just one fully working CCX and four cores with the same performance. The application would place each thead on a core and they'll be all equally fast.

With a six core processor, the operating system may place all four threads on four cores of a CCX, or may randomly place the threads across the two CCX. Therefore, whenever two threads of your application have to talk and exchange data between them, if they're across two CCX, they may be a bit slower.

So this application may actually be faster on the quad core processor than the six core processor because of this particularity.

 

If this was the case, there could be enough interest from programmers and compiler makers to add such Ryzen specific hacks to make threads always work on particular CCXes and quad core CPUs would be recommended over six or eight core CPUs for some tasks... it becomes a mess.

 

With Threadripper and EPYC there's more of these shenanigans... threads on same CCX are the best, then theres very small performance loss when threads between two threads on different CCX talk to each other within a die, then there's some much bigger performance loss when threads are across dies.

EPYC is the most affected but still, the speed is often much higher than Intel's speeds, see http://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd-epyc-7000-cpu-battle-of-the-decade/12

 

 

Pinned Memory Bandwidth (in MB/sec)
Mem
Hierarchy
AMD "Naples"
EPYC 7601
DDR4-2400
Intel "Skylake-SP"
Xeon 8176
DDR4-2666
Intel "Broadwell-EP"
Xeon E5-2699v4
DDR4-2400
1 Thread 27490 12224 18555
2 Threads, same core
same socket
27663 14313 19043
2 Threads, different cores
same socket
29836 24462 37279
2 Threads, different socket 54997 24387 37333
4 threads on the first 4 cores
same socket
29201 47986 53983
8 threads on the first 8 cores
same socket
32703 77884 61450
8 threads on different dies 
(core 0,4,8,12...)
same socket
98747 77880 61504

 

 

Quote

The new Skylake-SP offers mediocre bandwidth to a single thread: only 12 GB/s is available despite the use of fast DDR-4 2666. The Broadwell-EP delivers 50% more bandwidth with slower DDR4-2400. It is clear that Skylake-SP needs more threads to get the most of its available memory bandwidth.

Meanwhile a single thread on a Naples core can get 27,5 GB/s if necessary. This is very promissing, as this means that a single-threaded phase in an HPC application will get abundant bandwidth and run as fast as possible. But the total bandwidth that one whole quad core CCX can command is only 30 GB/s.

Overall, memory bandwidth on Intel's Skylake-SP Xeon behaves more linearly than on AMD's EPYC. All off the Xeon's cores have access to all the memory channels, so bandwidth more directly increases with the number of threads. 

 

Mem
Hierarchy
AMD EPYC 7601
DDR4-2400
Intel Skylake-SP
DDR4-2666
Intel Broadwell
Xeon E5-2699v4
DDR4-2400
L1 Cache cycles 4
L2 Cache cycles  12 14-22  12-15
L3 Cache 4-8 MB - cycles 34-47 54-56 38-51
16-32 MB - ns 89-95 ns 25-27 ns
(+/- 55 cycles?)
27-42 ns
(+/- 47 cycles)
Memory 384-512 MB - ns 96-98 ns 89-91 ns 95 ns

 

So you can see that as soon as threads have to exchange more than 8 MB of data between them, they can no longer use L2 and L3 caches to move data around (because each CCX has 8MB of cache) and the latency increases, while on Xeons the L3 cache is a big pool of data that is shared by all cores. That's the downside of using small dies and grouping cores in CCXes .. you get smaller easier to manufacture dies but there are some compromises.

 

In real world however, there's few apps which constantly move huge chunks of data between threads and even then, the performance loss compared to Xeons is not very big and often the lower price of AMD processors makes up for it.

 

-

 

So anyway, yeah back to the subject... yeah, Threadripper could be made with 10 cores... just make  3+2  + 3+2   ... same cores per die for same heat generation and even power consumption, same usage of memory caches and all that. There could be a bit of a mess with those CCX that have only 2 cores working but still have 8 MB of cache functional, those could work better than the threads on the other CCX with 3 threads and 8 MB of memory..

 

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16 hours ago, mariushm said:

So anyway, yeah back to the subject... yeah, Threadripper could be made with 10 cores... just make  3+2  + 3+2   ... same cores per die for same heat generation and even power consumption, same usage of memory caches and all that. There could be a bit of a mess with those CCX that have only 2 cores working but still have 8 MB of cache functional, those could work better than the threads on the other CCX with 3 threads and 8 MB of memory..

 

Good to know.  So a 10 core can exist.  The question is whether it will exist, and what the price would be.

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11 minutes ago, The Benjamins said:

ill put this here.

I new they would do a 8 core

At least it's not starved of PCIE lanes from the cpu like some other the other lower skew processors from competitors

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Just now, XenosTech said:

At least it's not starved of PCIE lanes from the cpu like some other the other lower skew processors from competitors

ya its a good PC got machines that need a lot of IO

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1 minute ago, The Benjamins said:

ya its a good PC got machines that need a lot of IO

Damn I just looked at the price... Up by $50 msrp from the 1800x

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Just now, XenosTech said:

Damn I just looked at the price... Up by $50 msrp from the 1800x

but the 4 channel DDR4 and PCIe with a clock bump makes it worth it

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1 minute ago, The Benjamins said:

but the 4 channel DDR4 and PCIe with a clock bump makes it worth it

That's still a steal of a deal either way

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9 minutes ago, The Benjamins said:

but the 4 channel DDR4 and PCIe with a clock bump makes it worth it

The 3.8/4.0 Ghz clocks are one of those "I wish the process was better" moments, haha.

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14 minutes ago, Taf the Ghost said:

The 3.8/4.0 Ghz clocks are one of those "I wish the process was better" moments, haha.

Yep, 3.8/4.8 would be amazing. If only.

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1 minute ago, leadeater said:

Yep, 3.8/4.8 would be amazing. If only.

AMD should run some of their processors through TSMC and see how crazy they can get with the clocks

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Just now, XenosTech said:

AMD should run some of their processors through TSMC and see how crazy they can get with the clocks

Yeah sure, after spending a few million dollars to adapt the 14nm design to 16nm and wait in line for nvidia's orders to be done and then spend months waiting for wafers to come out then validating chips for weeks then making microcode patches for the different "revision" cpu...

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9 minutes ago, mariushm said:

Yeah sure, after spending a few million dollars to adapt the 14nm design to 16nm and wait in line for nvidia's orders to be done and then spend months waiting for wafers to come out then validating chips for weeks then making microcode patches for the different "revision" cpu...

It's not meant to be sold to us... purely for in house testing

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1 hour ago, The Benjamins said:

but the 4 channel DDR4 and PCIe with a clock bump makes it worth it

The extra PCIe lanes alone is worth it.

49 minutes ago, leadeater said:

Yep, 3.8/4.8 would be amazing. If only.

Perhaps on zen+, or whatever they call it.

1 hour ago, The Benjamins said:

I new they would do a 8 core

An 8 core with 64 PCIe lanes for only 550.00?  Yes please!

The 1900x appeals to those that value expandability and doesn't need/cant afford more cores.

I'm only surprised because the 1900x kind of renders the 1800x obsolete.

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6 minutes ago, Cinnabar Sonar said:

The extra PCIe lanes alone is worth it.

Perhaps on zen+, or whatever they call it.

An 8 core with 64 PCIe lanes for only 550.00?  Yes please!

The 1900x appeals to those that value expandability and doesn't need/cant afford more cores.

I'm only surprised because the 1900x kind of renders the 1800x obsolete.

1800x has cheaper MOBO by $100-$300

 

it also has mATX and mITX boards

 

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23 minutes ago, The Benjamins said:

1800x has cheaper MOBO by $100-$300

 

True, although I would imagine that those who are on more of a budget, would choose the 1700/1700x instead.

Overclocking seems to get those two CPUs pretty close to the 1800x in clock speed.

Quote

it also has mATX and mITX boards

Yeah, mATX Threadripper is pretty pointless, and i'm not sure that the TR4 socket will even fit on a mITX board.:D

 

Edit: A 180 watt TDP might be a deal breaker for some...

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51 minutes ago, Cinnabar Sonar said:

True, although I would imagine that those who are on more of a budget, would choose the 1700/1700x instead.

Overclocking seems to get those two CPUs pretty close to the 1800x in clock speed.

Yeah, mATX Threadripper is pretty pointless, and i'm not sure that the TR4 socket will even fit on a mITX board.:D

 

Edit: A 180 watt TDP might be a deal breaker for some...

The 1900x has a xfr of 200 instead of the 100 on the 1800x

 

The 1900x seems it should hit 4ghz oc easily

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