Ryzen Threadripper Delidding

[Skanky Sylveon]

First off, damn!  That CPU did not want it's heat spreader removed.

Glad to see that Threadripper uses solder, i'm not surprised though.

What was surprising, was the fact that Threadripper has four dies.

That would mean that Threadripper is probably a reused EPYC CPU.  

Does this mean that we could see up to 32 cores on Threadripper if AMD wanted to?

[tom_w141]

repost

[Skanky Sylveon]

Just now, tom_w141 said:

repost

Sorry about that, I didn't see it.

[tom_w141]

Just now, Cinnabar Sonar said:

Sorry about that, I didn't see it.

I can't find it now. You might be ok if it got moved

[Skanky Sylveon]

Just now, tom_w141 said:

I can't find it now. You might be ok if it got moved

I didn't know whether this would be more appropriate in Tech News and Reviews or CPUs, Motherboards, and Memory

[leadeater]

27 minutes ago, Cinnabar Sonar said:

What was surprising, was the fact that Threadripper has four dies.

God dam called it! And people gave me shit about that lol.

[Skanky Sylveon]

5 minutes ago, leadeater said:

God dam called it! And people gave me shit about that lol.

People did?  It seems Perfectly logical to me.

[TetraSky]

Good to see AMD continuing to use Solder instead of pulling an Intel and using subpar TIM.

[rattacko123]

36 minutes ago, Cinnabar Sonar said:

People did?  It seems Perfectly logical to me.

It makes sense considering two of the dies are not functioning. If it was 4 functioning dies then there would be 128 pcie lanes instead of 64, that was one of the reasons why I thought threadripper would be 2 dies.

[leadeater]

38 minutes ago, Cinnabar Sonar said:

People did?  It seems Perfectly logical to me.

Yea, I originally thought that the TR rumors were just a few people mistaking it for Naples and the rest jumping on it. My reasoning for TR making no sense was that it wasn't justified to spend any R&D on making a different CPU package with two dies when you could literally just market Naples as a workstation CPU. So what actually happened is exactly what I thought it would be, Naples with different microcode.

[Skanky Sylveon]

Just now, leadeater said:

Yea, I originally thought that the TR rumors were just a few people mistaking it for Naples and the rest jumping on it. My reasoning for TR making no sense was that it wasn't justified to speed any R&D on making a different CPU package with two dies when you could literally just market Naples as a workstation CPU. So what actually happened is exactly what I thought it would be, Naples with different microcode.

Wasn't that more or less how the Intel HEDT CPUs came to be?

27 minutes ago, TetraSky said:

Good to see AMD continuing to use Solder instead of pulling an Intel and using subpar TIM.

Definitely.  Take notes Intel.  Solder, not mayonnaise!

3 minutes ago, rattacko123 said:

It makes sense considering two of the dies are not functioning. If it was 4 functioning dies then there would be 128 pcie lanes instead of 64, that was one of the reasons why I thought threadripper would be 2 dies.

I would imagine if four of the dies were functional, AMD would just have made it an EPYC chip.

[Dabombinable]

1 hour ago, Cinnabar Sonar said:

Wasn't that more or less how the Intel HEDT CPUs came to be?

Definitely.  Take notes Intel.  Solder, not mayonnaise!

I would imagine if four of the dies were functional, AMD would just have made it an EPYC chip.

Its not the same with Intel HEDT due to their insistence on using monolithic die since the start of the Core series (excluding the early generations having the iGPU on a separate die on a larger process)

And we already have examples of what's happened with the Ryzen 3: Half of the cores in each die aren't functional/are faulty, and AMD doesn't want to waste them.

[Skanky Sylveon]

1 hour ago, Dabombinable said:

Its not the same with Intel HEDT due to their insistence on using monolithic die since the start of the Core series (excluding the early generations having the iGPU on a separate die on a larger process)

Really?  Interesting, I would have assumed that Intel's HEDT chips where reject xeons.

2 hours ago, Dabombinable said:

And we already have examples of what's happened with the Ryzen 3: Half of the cores in each die aren't functional/are faulty, and AMD doesn't want to waste them.

It makes no sense to waste them, not when you can still sell them as cheaper, lower core CPUs.

[Drak3]

2 hours ago, Dabombinable said:

Its not the same with Intel HEDT due to their insistence on using monolithic die since the start of the Core series (excluding the early generations having the iGPU on a separate die on a larger process)

The big difference with Intel HEDT is that HEDT aren't necessarily reject processors being repurposed, but they are born as Xeon E5 processors. It's the same basic process as AMD's HEDT lineup, where server processors are getting consumer features, as an enthusiast platform.

[Liltrekkie]

4 hours ago, leadeater said:

God dam called it! And people gave me shit about that lol.

 

Only the smart ones knew this was basically a cut down EPYC chip with different microcode. 

 

On topic, and to address multiple people without quoting everyone who made this, It did not make sense to create a two die solution, not when they could use defective EPYC chips and reuse all the good cores across the various CCX's. It's either that, or each die is a 4 core chip, which would actually make tons of sense in terms of Threadripper, but I don't think its the case.

[Vode]

6 hours ago, leadeater said:

God dam called it! And people gave me shit about that lol.

Can't believe people did that.

 

People have no clue about engineering and business sometimes. lol

 

Why would AMD make a seperate SKU which at that high a price not many people would buy anyways.

[Bananasplit_00]

Nice, it would be fun if AMD drop an 18 core chip too right after Intel drops theirs just because 

[Morgan MLGman]

4 minutes ago, Bananasplit_00 said:

Nice, it would be fun if AMD drop an 18 core chip too right after Intel drops theirs just because 

I suspect if they wanted to beat Intel in terms of core count, I doubt it'd only be an 18 core Why not a 20-22 one?

[Bananasplit_00]

2 minutes ago, Morgan MLGman said:

I suspect if they wanted to beat Intel in terms of core count, I doubt it'd only be an 18 core Why not a 20-22 one?

Because that's where Epyc comes in. Just like with Intel where they don't want to cannibalize the Xeon sales, AMD don't want to impact Epyc sales

[Morgan MLGman]

11 minutes ago, Bananasplit_00 said:

Because that's where Epyc comes in. Just like with Intel where they don't want to cannibalize the Xeon sales, AMD don't want to impact Epyc sales

No, I meant that IF AMD wanted to beat Intel in the core count battle, they'd definitely have to make that TR at least a 20 core so it'd equal Intel's 18 core in performance. Unless the Intel 18-core will be clocked so low due to Kaby Lake not being nearly as efficient as Zen

 

Besides, following your core-count assumption TR already is about to impact lower-end EPYC sales:

[Skanky Sylveon]

1 hour ago, Vode said:

People have no clue about engineering and business sometimes. lol

 

It seems common sense to me, although admittedly I was surprised about the news myself.

19 minutes ago, Morgan MLGman said:

No, I meant that IF AMD wanted to beat Intel in the core count battle, they'd definitely have to make that TR at least a 20 core so it'd equal Intel's 18 core in performance. Unless the Intel 18-core will be clocked so low due to Kaby Lake not being nearly as efficient as Zen

 

AMD can, but why would they? 16 cores is already approaching server chip territory as it is.  The only reason that Intel released an 18 core chip is because they couldn't be seen as inferior to AMD.

Long story short, there probably isn't a huge market that would need more than 16 cores, and wouldn't be better off with EPYC.

[Taf the Ghost]

1 hour ago, VegetableStu said:

The EPYC and TR stack have cores in multiples of 4 so far. I'm not sure if AMD would want to disable a different number of cores on just one of the four CCXes ._.

 

20-core sounds more possible, maybe?

Engineering Samples showed up of split-count Cores (3+1 & 4+2), but AMD didn't want people sorting through CPUs to figure out which ones were busted. Plus it might cause some wonky performance problems. Current symmetrical system assures performance levels.

 

The TR version they delided is an ES, so it's possible they might not release the retail versions quite like this. Just with a placeholder under in the two spots.

 

I would also assume it's 1 good package per side. TR would be the Epyc CPUs with a faulty memory controller on one of the packages. Epyc requires that all 4 packages have a functioning memory controllers. This would explain how they can "use" >98% of dies on ~85% 8 core yields. Just make the die a spacer, haha. It got "used" at that point!

 

 

[Taf the Ghost]

41 minutes ago, Cinnabar Sonar said:

It seems common sense to me, although admittedly I was surprised about the news myself.

AMD can, but why would they? 16 cores is already approaching server chip territory as it is.  The only reason that Intel released an 18 core chip is because they couldn't be seen as inferior to AMD.

Long story short, there probably isn't a huge market that would need more than 16 cores, and wouldn't be better off with EPYC.

RAM controllers would be an issue with any further-up TR parts beyond 16c. It's possible the core choices is more because it'd break their microcode programmers trying to deal with the issues that would crop up.

[Taf the Ghost]

1 minute ago, VegetableStu said:

I dunno, if the methodology with R3 and R5 made sense for them, I don't see why they should bomb two CCXes (even if they leave the glass in there) when they could pick which core to disable. I would draw parallels on that at least ._.

Well, the Zen Package (2 CCX = 8 cores) costs them about $30 USD each. That's part of the reason their costs are so low. (Obviously R&D is a bit part of the end-user cost.) It seems strange to sack 2 full packages just to keep feed the TR pieces.

 

However, if a "bad" Zen package can be put on the interposer for TR and basically just act has a spacer, they've suddenly "saved" dead dies. At least some of them have bad memory controllers, and this is probably where they ended up.

[Taf the Ghost]

Though, honestly, if AMD can swing the Quad channel w/ 4 Zen Packages (which I actually think might be the issue), they really should think about selling a 32c TR part in the future. Just price it at $1999. Intel has clearly shown that $1999 USD "desktop" part is acceptable!