amd starship AMD's Starship CPU will contain 96 threads

[laminutederire]

9 hours ago, Curufinwe_wins said:

Uhh yes it is.

 

 

There isn't a metric out there that the Intel 14nm process is less dense than the competition. Also SRAM cell area is a very good approximation to transistor density, and by that metric Intel's 14nm process is almost 20% tighter than TSMC and 10% more dense than GloFlo/Samsung. The transistor density differences are actually larger than that.

 

http://www.extremetech.com/extreme/234681-intel-reportedly-wooing-apple-as-a-customer-for-its-arm-foundry-business

TSMC nodes are also supposed to be roughly 14% bigger than intel node on that spreadsheet. When you factor that into account, TSMC is relatively bigger than intel of less than 10% when compared to what is announced. Which means that Intel isn't crushing other people in terms of how they count nanometers, they count it roughly like TSMC.

[Coaxialgamer]

9 hours ago, Curufinwe_wins said:

Well 96 threads would be way behind Xeon Phi.... DoA behind... But a 48 core 2 way SMT or a 24 core 4 way SMT design could easily be imagined (with the latter probably being the most cost efficient to produce).

True,  but phi is using modified atom cores,  while amd is using the zen core on all market segments

[Notional]

9 hours ago, Curufinwe_wins said:

Uhh yes it is.

 

 

There isn't a metric out there that the Intel 14nm process is less dense than the competition. Also SRAM cell area is a very good approximation to transistor density, and by that metric Intel's 14nm process is almost 20% tighter than TSMC and 10% more dense than GloFlo/Samsung. The transistor density differences are actually larger than that.

 

http://www.extremetech.com/extreme/234681-intel-reportedly-wooing-apple-as-a-customer-for-its-arm-foundry-business

Remember your source critique. This is from Intel themselves. TSMC certainly does not agree:

 

 

Furthermore Intel has 3 sizes, depending on whether they are high density, low power or high performance. Samsung for instance has high density and high performance. They all differ in sizes, especially on the SRAM area.

 

Quote

Intel reported the following cell sizes:

High Density cell (6T-111) : 0.0499 µm2 (PU:PG:PD=1:1:1)
Low Voltage cell (6T-112) : 0.0588 µm2 (PU:PG:PD=1:1:2) 
High Performance cell (6T-123) : 0.0706 µm2 (PU:PG:PD=1:2:3)

So far as I know, the High Density cell is not used in any Intel products. The Low Voltage cell has been spotted in the LLCs of Xeon parts. I believe the CPU registers are built using the High Performance cells.

Samsung reported the following SRAM cell sizes:

High Density cell (6T-111) : 0.064 µm2 (PU:PG:PD=1:1:1)
High Performance cell (6T-122) : 0.080 µm2 (PU:PG:PD=1:2:2)

TSMC reported the following SRAM cell size:

High Density cell (6T-111) : 0.070 µm2 (PU:PG:PD=1:1:1)

Intel has the smallest node, but the difference is miniscule and heavily manipulated by Intel as well. The difference in gate pitch and sizes really aren't that different:

 

Do bear in mind that this is Samsung's/GloFO's 14nm FF Low Power Early. They use their Low Power Plus node now, which we don't know the specs of, other than it has higher performance (clock rate) and uses less power.

[Julian5]

13 hours ago, Electronics Wizardy said:

The problem is efficiency. It much better to have a ton of lower power cores than a few fast ones. 

 

These cpu's will be used in a server market were there running vm's, so the more the better when it comes to cores.

 

 

If you want fast cores, look at POWER and SPARC. Power8 currently has about 2x the IPC of intel and has 8 threads per core.

Sarcasm = msacras

[Tomsen]

13 hours ago, patrickjp93 said:

Intel's iGPU is bigger and more powerful than the A9 even on a Y SKU. The CPU is also more powerful. The cache is also much more powerful and of higher volume than Apple's cache.

 

TSMC's graph is shit and they know it. Intel countered it a long ago when they mocked their definition of 28nm and 20nm.

 

Intel does show off numbers. Do you not go to semiwiki or semiengineering? There are white papers from all the foundries, and Intel's 14nm definitely crushes the competition on characteristics. That doesn't change the fact Intel's CPUs are built for vastly higher performance, and control logic is the toughest to scale down because of its heat.

 

Actually Intel does use the exact same process across ALL of their product lines. https://www.quora.com/How-does-Intel-design-and-produce-so-many-models-of-CPUs

Well, what exactly are you comparing? Are you comparing a 15w tdp intel processor to a 3-5w tdp apple processor? IIRC, apple had higher graphic performance within the same power envolope. CPU performance varies. Cache is in the same volume.

 

It is as shit as Intels. Intel never countered afai. Lol patrick, it was every other foundry mocking intel for their definition of 22nm. 28nm been almost as dense as intel 22nm (or should I say 26nm)..

 

Patrick, once again you don't read what I'm writing. They don't disclose the transistor count of skylake-y. I don't visit them as frequent as I would.

Let me guess, the whitepapers show off the exact same numbers that Curufinwe_wins selected? If so, that by far doesn't tell the whole story.
We can also find some atoms to compare to, if you want something that isn't built for vastly higher performance. What will be the excuse then?

For ALL their product lines, or all their Core product lines? Are atoms (ultra low power) and xeon phi (HPC) using the exact same process, or using slightly modified for their case? Just because they don't disclosure how many variants of their 14nm process they have, doesn't mean the use the same for everything.

[Tomsen]

Btw, I didn't find any skylake-y transistor-count/area estimates, that I would count as eligible. It all was dirty math, as in subtract the amount of transistor a core has, and the area it occupies, but does not take things like uncore reductions and such into consideration.

[Prysin]

1 hour ago, Tomsen said:

Btw, I didn't find any skylake-y transistor-count/area estimates, that I would count as eligible. It all was dirty math, as in subtract the amount of transistor a core has, and the area it occupies, but does not take things like uncore reductions and such into consideration.

Let us compare, mobile SKUs with top end iGPUs then? How about 28 vs 14?
We know the size of the TSCM/GloFO 28nm by now, and Intel 14nm isnt a total enigma anymore either.... so how about that? its not too hard to find data on AMD and Intel mobile SKUs.

How about Bristol Ridge vs Skylake with Iris? We know these SKUs exist, even in the wild.

http://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks

http://www.anandtech.com/show/9990/skylake-iris-pro-hits-intels-pricing-lists-xeon-e3-1575m-v5-with-gt4e

http://ark.intel.com/products/93354/Intel-Xeon-Processor-E3-1575M-v5-8M-Cache-3_00-GHz

http://www.jagatreview.com/2016/06/hands-on-preview-amd-fx-9800p-bristol-ridge-apu-7th-gen/

 

Knowing how AMD APUs work, the transistor count and die sizes shown by GPU-Z is 85% of the time, the transistor count and size of the WHOLE SKU. Sometimes, this is not the case though, for unknown reasons.

 

So AMD managed 3100million transistors at 250mm2.... and the Xeon??? well i cannot find any data on that.

 

@patrickjp93

So here is your homework for monday. Find me total SKU transistor count for the Xeon E3-1575M-V5 WITH LINKS TO "PROOF". If links is behind "locked" sites, screen pictures uploaded to a image sharing site such as imgur.com will work just fine too.

 

 

[patrickjp93]

3 hours ago, Tomsen said:

Well, what exactly are you comparing? Are you comparing a 15w tdp intel processor to a 3-5w tdp apple processor? IIRC, apple had higher graphic performance within the same power envolope. CPU performance varies. Cache is in the same volume.

 

It is as shit as Intels. Intel never countered afai. Lol patrick, it was every other foundry mocking intel for their definition of 22nm. 28nm been almost as dense as intel 22nm (or should I say 26nm)..

 

Patrick, once again you don't read what I'm writing. They don't disclose the transistor count of skylake-y. I don't visit them as frequent as I would.

Let me guess, the whitepapers show off the exact same numbers that Curufinwe_wins selected? If so, that by far doesn't tell the whole story.
We can also find some atoms to compare to, if you want something that isn't built for vastly higher performance. What will be the excuse then?

For ALL their product lines, or all their Core product lines? Are atoms (ultra low power) and xeon phi (HPC) using the exact same process, or using slightly modified for their case? Just because they don't disclosure how many variants of their 14nm process they have, doesn't mean the use the same for everything.

All products for Atom to Xeon Phi use exactly the same process. Also, look again. Intel's Y series have far more cache than Apple's A9, and I mean the 4.5W chips as comparison.

 

Intel has released transistor counts for all of their products. You just have to know where to look.

[patrickjp93]

2 hours ago, Prysin said:

Let us compare, mobile SKUs with top end iGPUs then? How about 28 vs 14?
We know the size of the TSCM/GloFO 28nm by now, and Intel 14nm isnt a total enigma anymore either.... so how about that? its not too hard to find data on AMD and Intel mobile SKUs.

How about Bristol Ridge vs Skylake with Iris? We know these SKUs exist, even in the wild.

http://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks

http://www.anandtech.com/show/9990/skylake-iris-pro-hits-intels-pricing-lists-xeon-e3-1575m-v5-with-gt4e

http://ark.intel.com/products/93354/Intel-Xeon-Processor-E3-1575M-v5-8M-Cache-3_00-GHz

http://www.jagatreview.com/2016/06/hands-on-preview-amd-fx-9800p-bristol-ridge-apu-7th-gen/

 

Knowing how AMD APUs work, the transistor count and die sizes shown by GPU-Z is 85% of the time, the transistor count and size of the WHOLE SKU. Sometimes, this is not the case though, for unknown reasons.

 

So AMD managed 3100million transistors at 250mm2.... and the Xeon??? well i cannot find any data on that.

 

@patrickjp93

So here is your homework for monday. Find me total SKU transistor count for the Xeon E3-1575M-V5 WITH LINKS TO "PROOF". If links is behind "locked" sites, screen pictures uploaded to a image sharing site such as imgur.com will work just fine too.

 

 

Considering how much of that chip is an iGPU and a low performance ARM security processor, that's not impressive. It just goes back to saying : composition matters!

[Misanthrope]

So I'm assuming this is more of a CPU/GPU hybrid like Knight's landing right?

[Linus_torvalds]

21 hours ago, Electronics Wizardy said:

The problem is efficiency. It much better to have a ton of lower power cores than a few fast ones. 

Wrong! Look at iPhones and Android devices. It's 2 vs 4/6/8/10 cores, but we know who is faster

[Prysin]

Patrick, you know i like you, may even consider you an internet friend. But now you're being just a whiny lil bitch.

I gave you the opportunity to compare a Xeon with a GT4e iGPU, with eDRAM vs a 28nm dual module with iGPU and a small ARM core for security stuff... and you try to deflect the topic?

this is your GOLDEN FUCKING OPPORTUNITY TO PROVE YOU ARE RIGHT, and instead, you are just fanboying the fuck outta the whole "intel" part of the issue. Deflecting and obfuscating in a hope that nobody will follow up on it.

[Curufinwe_wins]

On 9/4/2016 at 6:28 AM, Notional said:

Snip

Couldn't reply to this cause forum bugginess, but basically here is my take on that. 

 

Let's assume Intel's statement is worst case, and tsmc is best case. That puts us in the range of 15-35% tighter. (Taking the numbers from TSMC's own plot). 

 

You will note I suggested the sram 6T cell is a decent rough approximation, and in that comparison it was 19.5% difference which is firmly in the middle of those two and perhaps more favorable to TSMC.

 

The fact remains that of the three foundries doing 14/16nm processes, Intel's is the tightest by a non-trivial margin (at these levels 15-35% is huge).

 

I mean Apple didn't decide to go with Intel fab for nothing after last gen dual sourcing the 14/16nm processes from TSMC and GloFo together.

 

I am not going to dispute the future 10nm and beyond process too much other than to suggest GloFo's proported timeline sounds hilariously unrealistic unless EUV magically fixes itself  (which based on everything we have seen from Intel, IBM, and TSMC isn't going to happen).

[Beskamir]

Honestly I can't see how this could even be possible let alone be better than fewer threads with more powerful cores. Multi-threading is difficult to get right so more cores/threads is usually pointless.

 

But then maybe I'm just an idiot and fail to realize the potential of these chips.

[patrickjp93]

15 minutes ago, ElfFriend said:

Honestly I can't see how this could even be possible let alone be better than fewer threads with more powerful cores. Multi-threading is difficult to get right so more cores/threads is usually pointless.

 

But then maybe I'm just an idiot and fail to realize the potential of these chips.

Have you never heard of OpenMP, CilkPlus, Thread Building Blocks, std::future, and std::async? They're all quite easy to use.

 

I mean, if you want to get fancy with asynchronous computing, you could even rig up HPX, but that's something you really only need on a massive cluster.

 

Now, under Amdahl's Law, the single core performance governs all, and honestly in mobile apps, multithreading is quite stupid, but that doesn't change the fact more is more.

[Beskamir]

1 minute ago, patrickjp93 said:

Have you never heard of OpenMP, CilkPlus, Thread Building Blocks, std::future, and std::async? They're all quite easy to use.

 

I mean, if you want to get fancy with asynchronous computing, you could even rig up HPX, but that's something you really only need on a massive cluster.

 

Now, under Amdahl's Law, the single core performance governs all, and honestly in mobile apps, multithreading is quite stupid, but that doesn't change the fact more is more.

Ah so I was just an idiot then . I only did basic Java threading in compsci so far and I'm going of the fact that most games/programs aren't really all that multi-threaded, but then that's probably outdated information when compared to computational situations which this cpu seems to be targeting.

[patrickjp93]

8 minutes ago, ElfFriend said:

Ah so I was just an idiot then . I only did basic Java threading in compsci so far and I'm going of the fact that most games/programs aren't really all that multi-threaded, but then that's probably outdated information when compared to computational situations which this cpu seems to be targeting.

Yeah, Java's threading library is quite antiquated. And games programmers are 10 years behind.

 

This is how you set up multithreading quick, dirty, readable, and still very effective

https://www.youtube.com/watch?v=nE-xN4Bf8XI&list=PLLX-Q6B8xqZ8n8bwjGdzBJ25X2utwnoEG

 

This is the bleeding edge of multithreading research: how you do it without having to use the fork-join model (coming to the C++ 17 standard in full glory, already implemented in std::experimental in most compilers)

 

[Tomsen]

On 9/4/2016 at 11:09 PM, patrickjp93 said:

All products for Atom to Xeon Phi use exactly the same process. Also, look again. Intel's Y series have far more cache than Apple's A9, and I mean the 4.5W chips as comparison.

 

Intel has released transistor counts for all of their products. You just have to know where to look.

Hm, I have just heard that intels -y series used their low-power process. I did, it still seems like apple is ahead. 4MB vs 4MB, it is the same amount of cache.

 

No they haven't, and  nearly every report specifially says Intel did not release transistor count on ALL their 14nm products. My guess is you don't where to look either since you don't bring any proof.

[patrickjp93]

2 minutes ago, Tomsen said:

Hm, I have just heard that intels -y series used their low-power process. I did, it still seems like apple is ahead. 4MB vs 4MB, it is the same amount of cache.

 

No they haven't, and  nearly every report specifially says Intel did not release transistor count on ALL their 14nm products. My guess is you don't where to look either since you don't bring any proof.

I posted proof. Between semiengineering, semiwiki, and Intel's own whitepapers available on their website and the International Supercomputing Conference papers, you can find them all.

 

Also, whoever told you there is a different process is full of crap, and Apple is not ahead.

[Tomsen]

1 minute ago, patrickjp93 said:

I posted proof. Between semiengineering, semiwiki, and Intel's own whitepapers available on their website and the International Supercomputing Conference papers, you can find them all.

 

Also, whoever told you there is a different process is full of crap, and Apple is not ahead.

You never posted any proof, patrick. Where is this thread have you posted the proof, link to that comment then. We have also been over why those whitepapers are useless, as simply covering the dimensions of merely a few pitches doesn't tell the whole story. 

 

For some reason I doubt that. I'm not saying apple is ahead (apple isn't a foundy), but that intels density advantages are greatly overestimated.