amd starship AMD's Starship CPU will contain 96 threads

[patrickjp93]

33 minutes ago, Curufinwe_wins said:

450mm is a pretty big die. BTW I wasn't thinking it was that amazing, it's just that is going to have to be a big die which at 7nm is going to be an exponentially larger cost than it would be even at 10nm.

 

Oh, I'm not saying Atom is bad... I was just saying it's smaller per unit core than the standard core arch (for obvious reasons). And that if this chip was a similar type approach then it would mean next to nothing since 72 core Phis are already available.

The big Haswell Xeon is 662 mm sq.

 

On 10nm the Xeon Phi vs. GPGPU game gets really interesting. 96 cores with 2 1024-bit vector units each at 1500MHz is 20.9 TFlops. That would eclipse the competition.

[Curufinwe_wins]

2 minutes ago, patrickjp93 said:

The big Haswell Xeon is 662 mm sq.

 

On 10nm the Xeon Phi vs. GPGPU game gets really interesting. 96 cores with 2 1024-bit vector units each at 1500MHz is 20.9 TFlops. That would eclipse the competition.

And that die was expensive.... A 10nm multipatterned EUV die (around 500 nm) is probably an order of magnitude more expensive to produce.

 

That will be interesting...

[Mira Yurizaki]

Sounds like AMD wants to get on the x86 compute bus to go against Xeon Phi. Or a massive server chip.

 

No reason for the average consumer to have 96 cores.

[Curufinwe_wins]

1 minute ago, M.Yurizaki said:

Sounds like AMD wants to get on the x86 compute bus to go against Xeon Phi. Or a massive server chip.

 

No reason for the average consumer to have 96 cores.

Well 96 threads would be way behind Xeon Phi.... DoA behind... But a 48 core 2 way SMT or a 24 core 4 way SMT design could easily be imagined (with the latter probably being the most cost efficient to produce).

[patrickjp93]

5 minutes ago, M.Yurizaki said:

Sounds like AMD wants to get on the x86 compute bus to go against Xeon Phi. Or a massive server chip.

 

No reason for the average consumer to have 96 cores.

96 threads*

 

It's only 48 cores.

[SansVarnic]

Believe it when I see it.

[Tomsen]

11 minutes ago, Curufinwe_wins said:

Uhh yes it is.

 

 

There isn't a metric out there that the Intel 14nm process is less dense than the competition. Also SRAM cell area is a very good approximation to transistor density, and by that metric Intel's 14nm process is almost 20% tighter than TSMC and 10% more dense than GloFlo/Samsung. The transistor density differences are actually larger than that.

 

http://www.extremetech.com/extreme/234681-intel-reportedly-wooing-apple-as-a-customer-for-its-arm-foundry-business

Uh no it is not.

 

Some dimension from a few pitches are far from telling the whole story of density.

 

Try look at some actual products transistor/mm^2. Good example is apple a8 vs core m. So much for intel been much much tighter..

 

Again this is not something new, intel have for a long time fidling with their nm numbers. The rest of the foundries just followed.

[Mira Yurizaki]

11 minutes ago, Curufinwe_wins said:

Well 96 threads would be way behind Xeon Phi.... DoA behind... But a 48 core 2 way SMT or a 24 core 4 way SMT design could easily be imagined (with the latter probably being the most cost efficient to produce).

Xeon Phi only implements a 4-way SMT to hide latency. In practice, the execution cores are tied up after two threads.

[Curufinwe_wins]

17 minutes ago, Tomsen said:

Uh no it is not.

 

Some dimension from a few pitches are far from telling the whole story of density.

 

Try look at some actual products transistor/mm^2. Good example is apple a8 vs core m. So much for intel been much much tighter..

 

Again this is not something new, intel have for a long time fidling with their nm numbers. The rest of the foundries just followed.

Show me those numbers on current gen products... I'd love to see them...

 

The SRAM cell design is not something that changes between the 3 nodes (they are all the classical 6T cells), so it is about as good as we have data to compare with atm.

 

GloFlo and TSMC "14/16nm" are literally finfet versions of their 20nm node, and are no denser.

Quote

 And in the past year, the use of node names has become even more confusing, as chip foundries prepare to roll out 14-nm and 16-nm chips, custom-made for smartphone makers and other customers, that will be no denser than the previous 20-nm generation. 

Source -> S. Wu (TSMC), 2013 IEDM, p. 224

http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated

[Curufinwe_wins]

3 minutes ago, M.Yurizaki said:

Xeon Phi only implements a 4-way SMT to hide latency. In practice, the execution cores are tied up after two threads.

Even at two threads the 48 core design is DOA in that market.

[Tomsen]

17 minutes ago, Curufinwe_wins said:

Show me those numbers on current gen products... I'd love to see them...

 

The SRAM cell design is not something that changes between the 3 nodes (they are all the classical 6T cells), so it is about as good as we have data to compare with atm.

 

GloFlo and TSMC "14/16nm" are literally finfet versions of their 20nm node, and are no denser.

Source -> S. Wu (TSMC), 2013 IEDM, p. 224

http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated

Kind of hard to give any numbers, when Intel no longer discloses them. Mm^2 is easy to get, but transistor count is harder. Funny how intel decided transistor count shouln't be disclosed with their 14nm..

 

SRAM cell is not the best meassurement for density.

 

Yeah, but you all seem to forget how far behind intel 22nm was. That is were the mistake is at.

 

I can go look for some estimates/meassurements of intel skylake-y 2+2 config SKU, but that will be a thing for tomorrow.

[Curufinwe_wins]

3 minutes ago, Tomsen said:

Kind of hard to give any numbers, when Intel no longer discloses them. Mm^2 is easy to get, but transistor count is harder. Funny how intel decided transistor count shouln't be disclosed with their 14nm..

 

SRAM cell is not the best meassurement for density.

 

Yeah, but you all seem to forget how far behind intel 22nm was. That is were the mistake is at.

 

I can go look for some estimates/meassurements of intel skylake-y 2+2 config SKU, but that will be a thing for tomorrow.

Yea because they actually got ahead of the competition there (they weren't before lol.) I mean they had new nodes out before others, but their nodes were less dense.

 

http://download.intel.com/newsroom/kits/14nm/pdfs/Intel_14nm_New_uArch.pdf Start at Slide 29-33. You could look at the previously cited paper instead, but it is actually the same data, and IDK if the paper was paywalled (I'm on a university VPN that automatically gets through most research paper paywalls, so I honestly wouldn't notice).

[patrickjp93]

32 minutes ago, Tomsen said:

Uh no it is not.

 

Some dimension from a few pitches are far from telling the whole story of density.

 

Try look at some actual products transistor/mm^2. Good example is apple a8 vs core m. So much for intel been much much tighter..

 

Again this is not something new, intel have for a long time fidling with their nm numbers. The rest of the foundries just followed.

That's a matter of composition and designing for super low power. You can pack more densely when you don't pack as hefty an iGPU as Intel and you don't have a 3-tier cache hierarchy.

 

No, Intel's are accurate. If you compare the iGPU density vs. the CPU density, they're different. Composition matters.

[patrickjp93]

3 minutes ago, Tomsen said:

Kind of hard to give any numbers, when Intel no longer discloses them. Mm^2 is easy to get, but transistor count is harder. Funny how intel decided transistor count shouln't be disclosed with their 14nm..

 

SRAM cell is not the best meassurement for density.

 

Yeah, but you all seem to forget how far behind intel 22nm was. That is were the mistake is at.

 

I can go look for some estimates/meassurements of intel skylake-y 2+2 config SKU, but that will be a thing for tomorrow.

Intel discloses it. The 6700K is 1.7 billion transistors. The transistor counts for the Broadwell Xeons are given too.

[patrickjp93]

33 minutes ago, M.Yurizaki said:

Xeon Phi only implements a 4-way SMT to hide latency. In practice, the execution cores are tied up after two threads.

Not true. Read the Xeon Phi optimization guide. With 2 threads you see 120% core performance and with 4 the top recorded performance is 154% vs. 1 thread. The engine is completely different from standard Hyperthreading.

[Tomsen]

5 minutes ago, Curufinwe_wins said:

Yea because they actually got ahead of the competition there (they weren't before lol.) I mean they had new nodes out before others, but their nodes were less dense.

 

http://download.intel.com/newsroom/kits/14nm/pdfs/Intel_14nm_New_uArch.pdf Start at Slide 29. You could look at the previously cited paper instead, but it is actually the same data, and IDK if the paper was paywalled (I'm on a university VPN that automatically gets through most research paper paywalls, so I honestly wouldn't notice).

If they got ahead, they would very much show the numbers. It is very much a sign of the opposite. It is not like it spoils intels secret to get to that density..

 

Those Intel slides have received some critic from TSMC, which made their own graph. Dont trust either it is pure marketing.

 

4 minutes ago, patrickjp93 said:

That's a matter of composition and designing for super low power. You can pack more densely when you don't pack as hefty an iGPU as Intel and you don't have a 3-tier cache hierarchy.

 

No, Intel's are accurate. If you compare the iGPU density vs. the CPU density, they're different. Composition matters.

Perhaps the reason I choose an equaliant SKU? Intel doesn't pack a hefty iGP in the SKU.

A8 does include l3 cache..

 

I didn't, you just did not read what i wrote.

 

4 minutes ago, patrickjp93 said:

Intel discloses it. The 6700K is 1.7 billion transistors. The transistor counts for the Broadwell Xeons are given too.

Look at your previous reply. This is pure bollocks from your side. Get me some stats of a skylake-y SKU.

[Curufinwe_wins]

2 minutes ago, Tomsen said:

snip

Uhh no. The 14nm node was so far beyond the hardest node ever produced yet (and the first one to make Intel slip on deadlines, which is something since they hadn't for nearly 20 years straight before). It makes perfect sense...

 

The 6700k is almost half IGPU.... and the cores themselves are like 1/4th of the die.

 

 

[Energycore]

2 minutes ago, Curufinwe_wins said:

Uhh no. The 14nm node was so far beyond the hardest node ever produced yet (and the first one to make Intel slip on deadlines, which is something since they hadn't for nearly 20 years straight before). It makes perfect sense...

 

The 6700k is almost half IGPU.... and the cores themselves are like 1/4th of the die.

That diagram begs a question. What process is the iGPU on? Is it also 14nm? And how much money could Intel save by making K SKUs without integrated graphics (which take some 30% of the die area)

[Curufinwe_wins]

Just now, Energycore said:

That diagram begs a question. What process is the iGPU on? Is it also 14nm? And how much money could Intel save by making K SKUs without integrated graphics (which take some 30% of the die area)

I don't remember if the igpu is on another process... It could be, but I don't see why it would be.

 

Xeon 1231v5 is basically the same price as a i5 so that is a good idea of how much (about 20%).

[Energycore]

1 minute ago, Curufinwe_wins said:

I don't remember if the igpu is on another process... It could be, but I don't see why it would be.

 

Xeon 1231v5 is basically the same price as a i5 so that is a good idea of how much (about 20%).

Dear Intel

 

(cheap) Overclockable Xeons plz!

[Tomsen]

3 minutes ago, Curufinwe_wins said:

Uhh no. The 14nm node was so far beyond the hardest node ever produced yet (and the first one to make Intel slip on deadlines, which is something since they hadn't for nearly 20 years straight before). It makes perfect sense...

 

The 6700k is almost half IGPU.... and the cores themselves are like 1/4th of the die.

 

 

That literally makes zero sense in any way. If it was the hardest node to date, you bet they woulf show off some numbers especially if ahead of competition. Do explain why they don't want to show off those innocent numbers.

 

Dont neither you and patrick read what I write? I try to compare equliant SKU from apple to intel. None of that desktop or xeon stuff.

 

skylake-y is what i will be looking for tomorrow.

[Curufinwe_wins]

2 minutes ago, Tomsen said:

That literally makes zero sense in any way. If it was the hardest node to date, you bet they woulf show off some numbers especially if ahead of competition. Do explain why they don't want to show off those innocent numbers.

 

Dont neither you and patrick read what I write? I try to compare equliant SKU from apple to intel. None of that desktop or xeon stuff.

 

skylake-y is what i will be looking for tomorrow.

Somehow the concept of trade secrets is foreign to you....

 

Derp...

 

The node isn't designed for the -y sku's (obviously), but go ahead and let us know what you see tomorrow.

[Tomsen]

Just now, Curufinwe_wins said:

Somehow the concept of trade secrets is foreign to you....

 

Derp...

 

The node isn't designed for the -y sku's (obviously), but go ahead and let us know what you see tomorrow.

Because those numbers modst definately reveals those trade secrets..

What did they do back in the day before, there were no trade secrets? Sorry that is a dumb excuse. Do explain how revealing those numbers (which used to be a standard precedure) would reveal trade secrets.

 

You sure they don't have some skylake-y process? Doubt they use the exact same process for all skylake SKU.

[bcredeur97]

1 hour ago, Curufinwe_wins said:

Uhh yes it is.

 

-snip-

There isn't a metric out there that the Intel 14nm process is less dense than the competition. Also SRAM cell area is a very good approximation to transistor density, and by that metric Intel's 14nm process is almost 20% tighter than TSMC and 10% more dense than GloFlo/Samsung. The transistor density differences are actually larger than that.

 

http://www.extremetech.com/extreme/234681-intel-reportedly-wooing-apple-as-a-customer-for-its-arm-foundry-business

I have always loved how thorough intel is with their designs. you can always tell a lot of effort goes into what they make (except for the cheap IHS thermal paste incident, but the actual dies/chips are amazing). 

 

Looking at this also makes me mad again that I got a TSMC chip in my iPhone 6S originally. It overheats occasionally in hot weather whereas the samsung chip one's do better with that. Also it's slightly more inefficient which on an iphone stinks, id love an extra 10-20 minutes of battery. It aint much but every bit counts.

[patrickjp93]

55 minutes ago, Tomsen said:

If they got ahead, they would very much show the numbers. It is very much a sign of the opposite. It is not like it spoils intels secret to get to that density..

 

Those Intel slides have received some critic from TSMC, which made their own graph. Dont trust either it is pure marketing.

 

Perhaps the reason I choose an equaliant SKU? Intel doesn't pack a hefty iGP in the SKU.

A8 does include l3 cache..

 

I didn't, you just did not read what i wrote.

 

Look at your previous reply. This is pure bollocks from your side. Get me some stats of a skylake-y SKU.

Intel's iGPU is bigger and more powerful than the A9 even on a Y SKU. The CPU is also more powerful. The cache is also much more powerful and of higher volume than Apple's cache.

 

TSMC's graph is shit and they know it. Intel countered it a long ago when they mocked their definition of 28nm and 20nm.

50 minutes ago, Energycore said:

That diagram begs a question. What process is the iGPU on? Is it also 14nm? And how much money could Intel save by making K SKUs without integrated graphics (which take some 30% of the die area)

It would cost them more as it would segment the manufacturing process for products that aren't any higher margin than their counterparts.

 

44 minutes ago, Tomsen said:

That literally makes zero sense in any way. If it was the hardest node to date, you bet they woulf show off some numbers especially if ahead of competition. Do explain why they don't want to show off those innocent numbers.

 

Dont neither you and patrick read what I write? I try to compare equliant SKU from apple to intel. None of that desktop or xeon stuff.

 

skylake-y is what i will be looking for tomorrow.

Intel does show off numbers. Do you not go to semiwiki or semiengineering? There are white papers from all the foundries, and Intel's 14nm definitely crushes the competition on characteristics. That doesn't change the fact Intel's CPUs are built for vastly higher performance, and control logic is the toughest to scale down because of its heat.

 

36 minutes ago, Tomsen said:

Because those numbers modst definately reveals those trade secrets..

What did they do back in the day before, there were no trade secrets? Sorry that is a dumb excuse. Do explain how revealing those numbers (which used to be a standard precedure) would reveal trade secrets.

 

You sure they don't have some skylake-y process? Doubt they use the exact same process for all skylake SKU.

Actually Intel does use the exact same process across ALL of their product lines. https://www.quora.com/How-does-Intel-design-and-produce-so-many-models-of-CPUs