AMD planning high-end CPU with all the bells and whistles

[Notree]

The 4670k is 20% faster than the 9590 from AMD in single threaded workloads. 40% increase in IPC would make it far better than what Intel is currently offering

Were talking clock for clock here. You can go look at the benchmarks. The info is out there. I'm not gonna argue with you.

[martinrox1568]

Were talking clock for clock here. You can go look at the benchmarks. The info is out there. I'm not gonna argue with you.

yea I completely forgot the 9590 came out of the box at 4.7ghz. For some reason I thought it's clockspeed was in the 4ghz range. I know IPC has nothing to do with clockspeed. I just thought for a split second that the 4770k and the 9590 had comparable frequencies

[LAwLz]

so.......pretty much the generic BS marketing/PR speak? nothing to actually show other than hopeful dreams?

 

moving on....

My reaction too. After all the bullshit regarding Bulldozer I no longer trust anything positive said from any company regarding their own products. The only thing that matters are replicable numbers from trusted third parties.

 

 

 

Also, I laughed a bit at 08:55.

"Some people harp on you, 'when are things going to change from 28nm or lower' but I don't really think right now that's really a relevant thing. Do you? I'm not really thinking that shrinking the die is like the most important thing right now. I think more power, cooler and efficient is more important than making smaller"

 

Doesn't Elric know that shrinking the die allows for more power, make the chip cooler and more efficient? People want to move away from 28nm because it will allow for faster, cooler and more efficient GPUs, not because the want cards to be smaller or whatever.

 

He gets corrected and admits that his viewers are right straight away but come on... How can you not know that Elric? It's like a really really basic thing.

[Valentyn]

This is a weird argument to make when 10-15 year old GPU's are still kicking around fully functional and your average PSU comes with 7 year warranty.

 

By the time these components die from usage, their performance is weak enough that you'd have taken them out years prior.

 

Very true! I still have a perfectly functional AMD 64 3200+ socket 754 system. The gainward 6600GT 265MB, and 400W Hyper PSU still work as well. Every works. Still have Guildwars 1 install on it.

 

I do AMD can become competitive on the CPU front again. I miss the days where it was hard to decide on what to buy.

[GoldSrc]

No, eDRAM and DDR4 aren't dissimilar. The difference is the stuff under the lid of your CPU is clocked higher and run in quad or octal channel to have both the benefits of low latency and high bandwidth without having to revise the memory controller of the CPU itself. And each level of cache serves a very specific purpose in the software pipeline. Throwing more cache at the problem solved nothing on its own and can make things worse. The larger the cache, the higher the latency to access it due to the internal search algorithms. For a CPU that's a precarious balance to maintain between bandwidth and latency. That's why the Crystalwell L4 cache only catches what falls out of L3 and does nothing else. For a graphics or compute workload with a larger data set than consumer CPU workloads and more memory reuse, you get the maximal benefit.

 

eDRAM is more expensive than RAM, and you know that, you can't really compare them.

 

 

Would it kill you to not run your mouth at people actually pursuing this field for a career? You're asking to get your butt handed to you.

 

There's no need for you to act like that you know.

That's not how you earn respect.

[vm'N]

My reaction too. After all the bullshit regarding Bulldozer I no longer trust anything positive said from any company regarding their own products. The only thing that matters are replicable numbers from trusted third parties.

 

 

 

Also, I laughed a bit at 08:55.

"Some people harp on you, 'when are things going to change from 28nm or lower' but I don't really think right now that's really a relevant thing. Do you? I'm not really thinking that shrinking the die is like the most important thing right now. I think more power, cooler and efficient is more important than making smaller"

 

Doesn't Elric know that shrinking the die allows for more power, make the chip cooler and more efficient? People want to move away from 28nm because it will allow for faster, cooler and more efficient GPUs, not because the want cards to be smaller or whatever.

 

He gets corrected and admits that his viewers are right straight away but come on... How can you not know that Elric? It's like a really really basic thing.

I like how they throw out useless numbers, like: 40% IPC increase

IPC have become purely a marketing term, with no actual value behind it. They know fanboys like the IPC term, so of course they will throw it out.

The videos I have seen with Elric, have also left me with the impression that he is less of an geek.

[othertomperson]

But that's just it, they wouldn't and won't because they see no value in doing so, and neither does anyone else in the industry. The Athlons are still as expensive as their APU counterparts most of the time.

 

I really don't care. I already have an Intel CPU without an iGPU, I'd get one again because I don't miss it.

[patrickjp93]

eDRAM is more expensive than RAM, and you know that, you can't really compare them.

 

 

 

There's no need for you to act like that you know.

That's not how you earn respect.

That's a matter of scale in production, not one of the actual difficulty or intricacy of its production. eDRAM is not necessarily expensive to make.

 

That's rich coming from you.

[jos]

That's a matter of scale in production, not one of the actual difficulty or intricacy of its production. eDRAM is not necessarily expensive to make.

 

That's rich coming from you.

SRAM is costlier than DRAM since SRAM uses more transistor to store a single bit than DRAM. eDRAM requires additional fab process steps compared with embedded SRAM, which raises cost, but the 3× area savings of eDRAM memory offsets the process cost when a significant amount of memory is used in the design. So costwise DRAM is cheaper. If you need more clarification please see transistor transistor logic and the fab required

[patrickjp93]

SRAM is costlier than DRAM since SRAM uses more transistor to store a single bit than DRAM. eDRAM requires additional fab process steps compared with embedded SRAM, which raises cost, but the 3× area savings of eDRAM memory offsets the process cost when a significant amount of memory is used in the design. So costwise DRAM is cheaper. If you need more clarification please see transistor transistor logic and the fab required

eSRAM is actually more difficult, which is why your L1 and L2 caches are so small. They're eSRAM, not eDRAM. eDRAM can never operate as fast as eSRAM, but it is much cheaper to make. Now, compared to the RAM used in DDR3 or DDR4, Intel's eDRAM is built on the 22nm FF process. The DRAM put in your DIMMS is built I believe still on 45 or 32nm planar. Intel gets a double density advantage which certainly offsets any additional costs to making conventional DRAM at this time, though it may not be the case at the same node sizes.

[FairladyZ]

If AMD pulls this off, they will really be in a good place. With the new Fury GPU and a new high end CPU, there could be a Titan X and 5960X killer build coming.

[patrickjp93]

If AMD pulls this off, they will really be in a good place. With the new Fury GPU and a new high end CPU, there could be a Titan X and 5960X killer build coming.

While the Titan X may very well be outmatched (not proven independently mind you, and I don't think we have watercooled Titan X benches yet, and AMD certainly didn't compare its scores with such a setup), for AMD to outmatch the 5960X would require both higher clock speeds and more cache (based on claimed 40% IPC improvement over Excavator and the clock cycle counts for Excavator vs. Haswell). If that is achieved, what will be the TDP? And, what about overclocking ability? The best 5960X are reaching to 4.6GHz and beyond on all 8 cores. For the Zen 8-core I'm betting close performance but being far cheaper and thus more palatable.

[WelshDdraig]

I know it sounds very fickle of me to say this, but I'm willing to switch platforms in a heartbeat.

I really hope that the future picks up for AMD. Fanboys may not like it, but they have to agree,

The industry needs competition, and it looks like AMD is trying to  bring it back.

[vm'N]

for AMD to outmatch the 5960X would require both higher clock speeds and more cache (based on claimed 40% IPC improvement over Excavator and the clock cycle counts for Excavator vs. Haswell). If that is achieved, what will be the TDP? And, what about overclocking ability? The best 5960X are reaching to 4.6GHz and beyond on all 8 cores. For the Zen 8-core I'm betting close performance but being far cheaper and thus more palatable.

You might want to explain your math.

What do you mean by "cycle counts"?

How do we pinpoint excavators and haswells IPC?

[Albatross]

I wish them all the luck in the world. They will need it.

[HarmFull]

ToT, Yay Elric

 

Glad to see AMD trying to compete again. Competition is good for the market, and our wallets :lol:

[patrickjp93]

You might want to explain your math.

What do you mean by "cycle counts"?

How do we pinpoint excavators and haswells IPC?

You do know every single instruction has a recorded latency in clocks available in the x86 manuals from Intel and AMD, right? It's even broken down by architecture. Taking that data it's not difficult to build an optimizing integer linear program where the fitness score is a normalized aggregate of open source benchmark scores (the theoretical CPU simulated on QEMU).

[vm'N]

You do know every single instruction has a recorded latency in clocks available in the x86 manuals from Intel and AMD, right? It's even broken down by architecture. Taking that data it's not difficult to build an optimizing integer linear program where the fitness score is a normalized aggregate of open source benchmark scores (the theoretical CPU simulated on QEMU).

Yes, but the individual instruction latency doesn't necessarily matter (as much as you would think), when different architectures, will be able to extract different amount of parallelism out of the IS, so you will end up in the same blind spot as before. So at best, your guess just leaves out a greater percentage-error.

[jos]

Yes, but the individual instruction latency doesn't necessarily matter (as much as you would think), when different architectures, will be able to extract different amount of parallelism out of the IS, so you will end up in the same blind spot as before. So at best, your guess just leaves out a greater percentage-error.

 

There are a large number of applications which limits itself to the amount of parallelism, so induvidual instruction lattencies are important for these apps... It is also for all tasks to be parallel \. there will be dependencies which also means per instruction cycles can be important. Parallelism is the way to go but classical thinking of programming has to be changed.. This very important if we think quantum computing area. 

[vm'N]

There are a large number of applications which limits itself to the amount of parallelism, so induvidual instruction lattencies are important for these apps... It is also for all tasks to be parallel \. there will be dependencies which also means per instruction cycles can be important. Parallelism is the way to go but classical thinking of programming has to be changed.. This very important if we think quantum computing area.

They don't limit themselves, they just become to dependency-prone or to branched.

A CPU is to complex, to try to derive any meaningful numbers out from a single isolated aspect.

Most instruction only takes a single cycle anyway for by far the most memory-operation + uop instructions.

[patrickjp93]

Yes, but the individual instruction latency doesn't necessarily matter (as much as you would think), when different architectures, will be able to extract different amount of parallelism out of the IS, so you will end up in the same blind spot as before. So at best, your guess just leaves out a greater percentage-error.

Not remotely true given we know exactly the functional units which will be used and thus the ILP possible (AVX 512 being 16-way for SP ints and floats). CISC really isn't as difficult to predict performance for as you say. 

 

Instruction latency matters quite a lot in any tasks which have many threads switching contexts, and it's still a direct way to calculate how many of that single operation may be performed in a single second or set number of cycles.

[jos]

They don't limit themselves, they just become to dependency-prone or to branched.

A CPU is to complex, to try to derive any meaningful numbers out from a single isolated aspect.

Most instruction only takes a single cycle anyway for by far the most memory-operation + uop instructions.

That is why i specifically mentioned dependencies and there are multtiple cycle istructions..just see the instruction sets

[Freshdoug]

Dat armpit sweat though. As a large sweaty man, I feel for this guy, 

[LAwLz]

Dat armpit sweat though. As a large sweaty man, I feel for this guy, 

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Can't really blame him. Of course he will be sweating like crazy. He is in the same room as an AMD graphics card.

[ErickS89]

I have no problem upgrading my motherboard and cpu, I hope it's a monster!