AMD planning high-end CPU with all the bells and whistles

[Colonel_Gerdauf]

Can't really blame him. Of course he will be sweating like crazy. He is in the same room as an AMD graphics card.

 

That makes me wonder, how many 390X's will it take to make a functional stove sauna?

[Sakkura]

That makes me wonder, how many 390X's will it take to make a functional stove sauna?

 

Something like 20 for a typical sauna. I wouldn't recommend throwing water on them like you would in a normal sauna though.

[CaptainGazzz]

The amount of shots fired from AMD is too high in this video.

[vm'N]

Not remotely true given we know exactly the functional units which will be used and thus the ILP possible (AVX 512 being 16-way for SP ints and floats). CISC really isn't as difficult to predict performance for as you say. 

 

Instruction latency matters quite a lot in any tasks which have many threads switching contexts, and it's still a direct way to calculate how many of that single operation may be performed in a single second or set number of cycles.

And there is no logic behind it? Only simple execution?

Are zen even been confirmed to support AVX512?

No, might not be that hard, if you only use one certain kind of execution unit, with no real logic behind it?

But does it tell anything about its general performance?

That would be alot of threads running some complex CISC instructions (those who are often have more than few cycles latency). You would be stressing the frontend, to such an extent, it would bottleneck the backend. Of course instruction latency matters, but the most important instruction latency already have a decently low latency. This was done before super-scalar was introduced, and was a way to optimize the serial instruction execution. I'm not saying it doesn't matter, I'm saying that the most important of it have already been done.

 

That is why i specifically mentioned dependencies and there are multtiple cycle istructions..just see the instruction sets

I never said there werent instructions with higher cycles latency.

[patrickjp93]

And there is no logic behind it? Only simple execution?

Are zen even been confirmed to support AVX512?

No, might not be that hard, if you only use one certain kind of execution unit, with no real logic behind it?

But does it tell anything about its general performance?

That would be alot of threads running some complex CISC instructions (those who are often have more than few cycles latency). You would be stressing the frontend, to such an extent, it would bottleneck the backend. Of course instruction latency matters, but the most important instruction latency already have a decently low latency. This was done before super-scalar was introduced, and was a way to optimize the serial instruction execution. I'm not saying it doesn't matter, I'm saying that the most important of it have already been done.

I never said there werent instructions with higher cycles latency.

AVX 512 is confirmed for Zen by AMD. I didn't say I was only using one functional unit, and I know AMD's build logic extensively. AMD is using an independent dual-256 FMAC in each core, so you can run 2 256 extensions per core or 1 512 extension. It's a bulkier design that will take some burden away from the OOOP engine since 512 use will be rare outside HPC and in HPC will be used as much as possible. You underestimate what we already know about Zen. It's going to wind up with Haswell per-clock performance clock speed remains the only variable.

You're also incorrect regarding instruction late comes. Even Intel's add/sub/mul/div instructions take about 60 cycles. There's plenty of room to shrink that.

[vm'N]

AVX 512 is confirmed for Zen by AMD. I didn't say I was only using one functional unit, and I know AMD's build logic extensively. AMD is using an independent dual-256 FMAC in each core, so you can run 2 256 extensions per core or 1 512 extension. It's a bulkier design that will take some burden away from the OOOP engine since 512 use will be rare outside HPC and in HPC will be used as much as possible. You underestimate what we already know about Zen. It's going to wind up with Haswell per-clock performance clock speed remains the only variable.

Have AMD actually confirmed AVX512 support? I haven't seen any official confirmations yet.

You only mentioned one kind of execution unit, and one kind of workload.

I was more concerned with the software logic, ie that there are a purpose with the program, and you are not just doing simple execution.

That is the culprit.

Now, it wouldn't surprise me, if AMD went with dual 256bit pipelines to execute 512 instructions (if the end up supporting AVX512), but have it actually been confirmed? I remember the "leaked" block-diagram of zen. The problem with having dual pipelines, it can create port-confliction on heavier workloads (especially when they now have implemented SMT). But again, they probably find a way, to lessen the work on certain ports, and try to divide it up evenly, so you can still run a mixed workload, without having to prioritize something over the other.

What do we know? That it support AVX512? That is what you have based your calculations off, as far as I know. I have already asked into your math, so you are more than welcome to demonstrate your knowledge.

We also know that haswell have 70-100% better per-clock performance over ivy  :rolleyes:

 

You're also incorrect regarding instruction late comes. Even Intel's add/sub/mul/div instructions take about 60 cycles. There's plenty of room to shrink that.

The most optimization to instruction latency was done, before we implemented some sort of ILP. Because at this time, it was one of the critical factors in terms of performance (it have a much smaller effect today, as we have added layers upon layers to extract more performance).

IIRC only divs should take that long for the regular arithmetic instruction. Mul should be shorter, and add/sub should be even shorter.

IIRC the reason for this huge latency (compared to other arithmetic instruction) was because how div was calculated (should be similar to sqrt).

[IMPERIUS]

Whats it gonna have? 2 times the core number of intel?

[SurvivorNVL]

Well, Skylake shall hold me over until Zen.  Wish it were out sooner.  Would love to see not only the performance and pricing, but also the motherboards.  And you know there'll be some AMD branded DDR4 ram in the future.

[patrickjp93]

Well, Skylake shall hold me over until Zen.  Wish it were out sooner.  Would love to see not only the performance and pricing, but also the motherboards.  And you know there'll be some AMD branded DDR4 ram in the future.

It really is unfortunate AMD is looking at a Q2/Q3 2016 release date for Zen.

[SurvivorNVL]

It really is unfortunate AMD is looking at a Q2/Q3 2016 release date for Zen.

Yeah.  Wish it were sooner, but then again--hopefully it will be a home run for them.  Skylake will hold me over, unless Skylake-E is far more spectacular than Zen.  I just want to reach an 8-core that OC's well and is below $1000.

[BOT Edward]

ADD MORE CORES!!!!

[SImoHayha]

I need a new CPU hopefully they will have a nice stronger AM3+ cpu for me.................

[Ketcchup]

Welcome to March/May 2015

[niofalpha]

I need a new CPU hopefully they will have a nice stronger AM3+ cpu for me.................

AM3+ Is dead no new non-refreshed CPU's, confirmed months ago. 

[harrybob141]

Unfortunately, When this drops, intel will counter with a better CPU, the reason they haven't is because they don't need to.

[Khvarrioiren]

Unfortunately, When this drops, intel will counter with a better CPU, the reason they haven't is because they don't need to.

 

Which isn't actually a bad thing, because they'd finally have to, meaning that the competition is ramping up. I don't hold my hopes high enough for Zen to foresee that happening, though.

 

Actually, I hold no hopes at all that Zen is able to compete with Skylake and future Intel architectures  in any other category than mid-high-end price/performance.