TSMC Clarifies Apple's UltraFusion Chip-to-Chip Interconnect

[DANK_AS_gay]

Summary

 TSMC described exactly how Apple has engineered the "UltraFusion" chip interconnect. It seems to be an expensive, relatively complicated way to achieve chip interconnection, but with the added benefit of ridiculous speeds.

 

 

Quotes

Quote

Ultimately, Apple's UltraFusion chip-to-chip interconnect uses a passive silicon bridge that connects one M1 Max to another M1 Max processor to build an M1 Ultra, but there are several ways to implement such a bridge. InFO_LI uses localized silicon interconnects beneath multiple dies instead of large and costly interposers, which is a concept that is very similar to Intel's embedded die interconnect bridge (EMIB).  

 

My thoughts

 I would never have thought that Apple would let this info leak, and I find it interesting that they did not completely reinvent the wheel here. I wonder if Apple will use this later, and why. (Besides a future Ultra chip, or maybe even a desktop chip)

 

Sources

https://www.tomshardware.com/news/tsmc-clarifies-apple-ultrafusion-chip-to-chip-interconnect  

 

[DANK_AS_gay]

I didn't say a ton on this as I am not a silicon manufacturing engineer. I cannot give my opinions on something I do not know. I find it interesting, but It doesn't realistically have that much of an impact on the PC space, besides maybe Apple making a more tileable design to make manufacturing cheaper.

[porina]

10 minutes ago, DANK_AS_gay said:

 I would never have thought that Apple would let this info leak, and I find it interesting that they did not completely reinvent the wheel here. I wonder if Apple will use this later, and why. (Besides a future Ultra chip, or maybe even a desktop chip)

I'm not sure Apple have any say in it. This would appear to be a TSMC tech. Apple are merely a user of it, in a similar way to AMD's 3D cache. Now, have TSMC outright said this is what Apple uses? That might be a confidentiality thing, but they can certainly talk about their tech in a general way, not necessarily customer specific way.

 

Just quickly looking at the diagram, it would look more advanced than EMIB to me. EMIB being more of an edge interconnect whereas this looks to be a whole layer, increasing the connectivity potential.

[DANK_AS_gay]

2 minutes ago, porina said:

I'm not sure Apple have any say in it. This would appear to be a TSMC tech.

Nvm, I read it wrong.

[hishnash]

1 hour ago, DANK_AS_gay said:

 I would never have thought that Apple would let this info leak, and I find it interesting that they did not completely reinvent the wheel here. I wonder if Apple will use this later, and why. (Besides a future Ultra chip, or maybe even a desktop chip)

 

Once a product has shipped sharing info about the product even detailed info like this is not considered a leak by apple. Apple staff are only prohibited from sharing info about future products.  Apple really have no issue with someone confirming a given bit of tec in an existing shipping product. 

[GOTSpectrum]

I really want to see someone integrate a L3 or L4 cache on the interconnect later. AFAIK they are silicon wafers, so they should be able to have gates. Would be an interesting way to make the compute chip smaller, ans also move the cache to the lower section of the package so heat can be better managed for the compute side of things. The biggest issue i can think of is how you would get that level of wattage through multiple layers to the compute dies. 

 

This could be even more interesting for GPUs which should have larger dies and thus more space on their interconnect layer for things like cache. 

 

I dunno, I'm not a silicon engineer and they are probably reasons its not been done. But imagine if you could even have certain IO logic integrated in the lower die. Hell fab the lower die in 7nm or 12nm and have the compute elements be 5nm or whatever it is we are up to now. 

[DANK_AS_gay]

3 minutes ago, GOTSpectrum said:

7nm or 12nm

(depending on the manufacturer) Don't they throw out older machines?

[GOTSpectrum]

5 minutes ago, DANK_AS_gay said:

(depending on the manufacturer) Don't they throw out older machines?

not usually, the older machines are in use for many projects like the chips in cars, IOT devices, coffee machines ect ect 

 

I'm pretty sure you can still order 12 and probably older nodes from TSMC/

 

GloFo still operates and only had 12nm and older nodes so even if not TSMC you have glofo as an option. 

[DANK_AS_gay]

1 minute ago, GOTSpectrum said:

not usually, the older machines are in use for many projects like the chips in cars, IOT devices, coffee machines ect ect 

 

I'm pretty sure you can still order 12 and probably older nodes from TSMC/

 

GloFo still operates and only had 12nm and old nodes so even if not TSMC you have glofo as an option. 

Honestly, if it hasn't been done, it's either been done in an engineering sample, or the accountants shut the idea down. Or both.

[Dracarris]

7 minutes ago, DANK_AS_gay said:

(depending on the manufacturer) Don't they throw out older machines?

Hello no! There are still nodes like 65, 90, 130 and even 180nm in widescale active production today.

[DANK_AS_gay]

1 minute ago, Dracarris said:

Hello no! There are still nodes like 65, 90, 130 and even 180nm in widescale active production today.

180NM!!! WTF! Who needs that??? My Pentium III is that node! Welcome back to 1999. Geez.

[Dracarris]

12 minutes ago, DANK_AS_gay said:

180NM!!! WTF! Who needs that??? My Pentium III is that node! Welcome back to 1999. Geez.

All the 16-48MHz low power MCUs found in every tool/toy/washing machine use such process nodes. Dirt cheap, low leakage, near 100% yield, readily available and sufficient delays/timing.

Also for pure analog chips the node is quite irrelevant since analog doesn't really scale. Older nodes with higer intrinsic gain and unit capacitance are even easier to design for.

[leadeater]

9 minutes ago, Dracarris said:

Also for pure analog chips the node is quite irrelevant since analog doesn't really scale.

Analog in a lot of cases actually requires those larger node sizes. Same goes for extreme high power and/or voltage MOSFETs.

[Dracarris]

4 minutes ago, leadeater said:

Analog in a lot of cases actually requires those larger node sizes. Same goes for extreme high power MOSFETs.

yes, or for RF. Porting analog to a smaller node due to a large digital circuit that needs to be integrated often basically requires a re-design of a significant portion. Sometimes transistors are not available for the required voltages, so you have to stack them and make sure the voltage over one never exceeds spec and so and so on..

 

@DANK_AS_gay here is some info:https://www.smics.com/en/site/mature_logic

These processes apparently get labeled "mature".

[leadeater]

4 minutes ago, Dracarris said:

yes, or for RF.

I was lumping RF in with Analog, I probably shouldn't do that 

[DANK_AS_gay]

What the heck is going on? I knew old nodes were being used in cars, but I always thought that the oldest node people still make would be 28nm, simply because of the Atom processors. I also didn't know that analog stuff was still on the scale of nodes, that's crazy! 

[leadeater]

2 minutes ago, DANK_AS_gay said:

What the heck is going on? I knew old nodes were being used in cars, but I always thought that the oldest node people still make would be 28nm, simply because of the Atom processors. I also didn't know that analog stuff was still on the scale of nodes, that's crazy! 

Silicon transistors do more than logic circuits which is all a CPU is. Flipping states of switches, just lots of them at massive scale, billions. Something like a power MOSEFT is a single transistor that need to handle whatever the design load is. So for a CPU VRM MOSFET it needs to handle 12V and up to say 100A. Or on the higher end MOSFET for 600V 801A, some tiny wee  7nm or 28nm could simply not handle that at all.

[Dracarris]

33 minutes ago, leadeater said:

I was lumping RF in with Analog, I probably shouldn't do that 

RF is a very special kind of analog, one that most are not aware of with few capable designers on the market - yet it is crucial to keep every phone going.

33 minutes ago, DANK_AS_gay said:

What the heck is going on? I knew old nodes were being used in cars, but I always thought that the oldest node people still make would be 28nm, simply because of the Atom processors. I also didn't know that analog stuff was still on the scale of nodes, that's crazy! 

Even for 28nm, designing and prototyping is still very expensive and many applications simply don't need the speed and transistor density. Scaled nodes offer to pack many minimum-size, independent transistors very densely and offer reduced gate and wire capacitances, so faster switching with less power. That's very welcome for digital compute but not for every use case as leadeater already explained.

[porina]

8 hours ago, GOTSpectrum said:

I'm pretty sure you can still order 12 and probably older nodes from TSMC/

7nm and smaller probably passed 50% of TSMC's revenue recently. Still a lot of older nodes going on.

 

12nm isn't broken out in that chart, probably bundled with 16nm since 12nm was a high density version of that.

[leadeater]

9 hours ago, GOTSpectrum said:

I really want to see someone integrate a L3 or L4 cache on the interconnect later.

Wouldn't be surprised if in the near future AMD has no L3 cache on the CCD die and it's only stacked (above or below).

[Doobeedoo]

I wonder will they go merging like 4 of them with active bridge or no. They will scale more we know.

[GOTSpectrum]

3 hours ago, leadeater said:

Wouldn't be surprised if in the near future AMD has no L3 cache on the CCD die and it's only stacked (above or below).

I can also see this. I just want to see someone utilize the interconnect layer better. Think how much cache you could fit on a large say 14 or even 28nm interconnect die on EPYC. 

 

That or/and throw a stack of HBM...3... are we at 3 yet? on the package with EPYC, would be an interesting beast and for the right work loads would be pretty insane 

[leadeater]

2 hours ago, GOTSpectrum said:

That or/and throw a stack of HBM...3... are we at 3 yet? on the package with EPYC, would be an interesting beast and for the right work loads would be pretty insane 

On package HBM is already coming with the next Intel Xeons, which are coming real soon.