Raja Koduri shows Ponte Vecchio (Xe HPC) package, That's a lot of chiplets.

[AlexGoesHigh]

On twitter Raja Koduri, one of intel top engineers posted a picture of the silicon package of Ponte Vecchio. The largest GPU in the entire Xe family that's meant for datacenters and supercomputers, its also the part of the compute stack for the Aurora supercomputer. Raja says that the package is composed of 7 different silicon technologies such as Intel Foveros, EMIB, 10nm superfin and next gen 7nm also others technologies are third party silicon process such as the IO link.

 

 

 

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The post comes about as intel is gonna do the first power on test for Ponte Vecchio, an important milestone in chip design.

 

That's a lot of glued on chips for a company that once called glued on chips inferior... Memes and trolling aside that's honestly amazing and its a short post but anyways i think is interesting for the fact that Intel is placing a lot of different tech in order to make a giant GPU for compute. In comparison first gen EPYC was four dies in a package. 2nd gen EPYC, the up to 64 core behemoth that crushed intel, goes up to 8 7nm chiplets and 1 IO die in the middle and here Intel is one step closer to releasing this beast that built on 7 different silicon technologies.

 

Sources

https://www.anandtech.com/show/16453/intel-teases-ponte-vecchio-xehpc-power-on-posts-photo-of-server-chip

[jaslion]

I hope that because there are so many chiplets they avoided getting too much latency between them. If they do have a lot of latency they should probably look at their glue quality :p.

[Rugg]

So the 8 squares on the edges are core chilpets, the big center is IO, and what are the thin rectangles on the corners?

[leadeater]

40 minutes ago, Rugg said:

So the 8 squares on the edges are core chilpets, the big center is IO, and what are the thin rectangles on the corners?

My guess is the two large chips in the middle are the GPU elements, the 8 chips around those are HBM and the two in diagonally opposite corners are....???

[leadeater]

7 minutes ago, gabrielcarvfer said:

IO?

Possibly, would be an odd choice if there is only 1 large GPU chip per IO chip though, would be rather bandwidth and connectivity limiting for not much gain unless they plan on updating the GPU chips faster or have many different ones etc.

 

Might be a high speed low latency L4 cache maybe, like RNDA2 but off chip on package from the main GPUs.

[spartaman64]

they seriously named it rambo cache? LUL

[AlexGoesHigh]

This is just me going on what i think make sense so i could be completely wrong but i think this is what the chips layout could be.

 

 

Another good posible layout is swap Rambo cache and IO/Base chips, thoughts? 

[HenrySalayne]

Is this how the final product is supposed to look like or is it just a sample to test it? The tightly packed, rectangular and perfectly symmetrical part in the middle looks like it might be just one die in the future. Any idea about the size of this thing?

 

Edit: Size estimation considering 0402 and 0201 caps (might be completely wrong).

[StDragon]

4 hours ago, gabrielcarvfer said:

Intel should be considered an adhesive company after this much glue.

At least they stopped sniffing it. Impressive! That chip ain't no Dorito!

[StDragon]

3 hours ago, spartaman64 said:

they seriously named it rambo cache? LUL

Because a cache-miss is its worst nightmare??

[Dutch_Master]

5 hours ago, gabrielcarvfer said:

HBM/Rambo cache?

Sylvester Stallone wants to know your location! One NEVER puts HBM and Rambo in the same sentence!

 

[Dutch_Master]

3 hours ago, HenrySalayne said:

Is this how the final product is supposed to look like or is it just a sample to test it? The tightly packed, rectangular and perfectly symmetrical part in the middle looks like it might be just one die in the future. Any idea about the size of this thing?

 

Edit: Size estimation considering 0402 and 0201 caps (might be completely wrong).

That's one heck of a chip, dunno exactly how big EPYC/TR chips are, but this is probably bigger. Although, should the rumours about AMD's upcoming 7000 series GPUs have any merit on the chiplet design, these Intel Xe chips may not be the biggest GPU chips for long!

[HenrySalayne]

14 hours ago, HenrySalayne said:

Is this how the final product is supposed to look like or is it just a sample to test it? The tightly packed, rectangular and perfectly symmetrical part in the middle looks like it might be just one die in the future.

I just realized the tidy looking part in the middle is the Foveros package. It is a single die with a whole bunch of additonal tiny dies on top. This means the tiny dies on top are not IO dies but rather compute cores or cache "tiles". It would be interesting to know how the chip will be cooled and if it is possible to directly put pressure on this structure or if it needs an IHS to work. It looks rather fragile to be honest.

 

10 hours ago, Dutch_Master said:

That's one heck of a chip, dunno exactly how big EPYC/TR chips are, but this is probably bigger

The Threadripper/EPYC package size is 58.5 mm × 75.4 mm, so it's roughly in the same ball park if I'm not mistaken.

[Dr_Whom]

50 minutes ago, HenrySalayne said:

I just realized the tidy looking part in the middle is the Foveros package. It is a single die with a whole bunch of additonal tiny dies on top. This means the tiny dies on top are not IO dies but rather compute cores or cache "tiles". It would be interesting to know how the chip will be cooled and if it is possible to directly put pressure on this structure or if it needs an IHS to work. It looks rather fragile to be honest.

All of the earlier teases for it show it with an IHS. Doesn't answer your question on whether it requires the IHS or not, but it does have one.

 

[RejZoR]

It has IHS because everyone knows Linus and Raja drop everything. So they need to put a shield over the actual chips

[leadeater]

9 hours ago, RejZoR said:

It has IHS because everyone knows Linus and Raja drop everything. So they need to put a shield over the actual chips

Then wouldn't it be an IDS? Integrated Drop Shield

[linuxChips2600]

3 minutes ago, leadeater said:

Then wouldn't it be an IDS? Integrated Drop Shield

@LinusTechshould be invited to test that

[linuxChips2600]

On 1/26/2021 at 3:09 PM, jaslion said:

I hope that because there are so many chiplets they avoided getting too much latency between them. If they do have a lot of latency they should probably look at their glue quality :p.

 

On 1/26/2021 at 3:11 PM, gabrielcarvfer said:

Intel should be considered an adhesive company after this much glue.

Don't forget that Navi was "Koduri's pet project" (https://www.pcgamer.com/amd-reunites-raja-koduri-with-his-baby-an-rx-6800-graphics-card/)...
 

Intel (probably) went "the way of the glue (™ pending)" after getting Threadripper™-ed by AMD...

btw no joke; for real how would one go about trademarking a phrase/slogan/etc.?

[linuxChips2600]

7 minutes ago, linuxChips2600 said:

@LinusTechshould be invited to test that

Before anyone calls me out for tagging the main man himself... think about all the P U B L I C I T Y that such an invitation can generate if done properly... It'd be kinda cool too to interview someone who is now (afaik, at least partly) responsible for driving innovation behind two competing semiconductor giants. (video idea anyone?)

[RejZoR]

Did they actually call that cache "Rambo Cache" lol? What is it going to do, slice some necks and cut some trees with M60 ?

[porina]

I really wonder why there are two different shaped HMB dies... any ideas?