I made this RAM you’ve never seen before - Micron Factory Tour (SPONSORED)

[BellLMG]

Thanks to Micron for sponsoring this video! Learn more about how Crucial by Micron can make upgrading your setup easy by checking them out at: http://crucial.gg/LTT

 

Linus doesn't travel for projects often anymore, but when Micron invited him out to their 200,000 sq. ft. facilities in Boise, Idaho to make his own RAM from scratch, he knew that he had to go. Making RAM isn't easy, so sit back and take a look at how RAM goes from raw components to powering the device you're watching this on!

 

 

 

[darknessblade]

Micron takes the concept of a motherboard/PCB wall to a whole other level

[05032-Mendicant-Bias]

Linus now has the most bleeding edge consumer ddr5 in the hemisphere. Good for him.

That was an enjoyable and informative video, it was a blast seeing those enormously expensive new machines. At the uni we saw decades old machines for I think 1um CMOS process.

[WarbossChoppa]

I think he made stacked single rank DDR5 8800 dimms that Micron has been teasing on their website for a bit.

[ToboRobot]

From an audio perspective, during factory tours with industrial background noise having background music as well is slightly distracting.  Either cut the music, or just re-record the voiceovers in post so we don't have the factory background noise.

[Alcarin]

God that was a fascinating video. Chip fabrication has always been super interesting to me, but I highly doubt I'll ever qualify for even an entry-level position in a lab tbh.

 

While attending BSU, I lived about 2 miles away from this Micron campus.

 

This video is no doubt one of, if not the best, videos LMG has done in at least the past year or so IMHO. 10/10 big success.

[fawncashew]

1 hour ago, WarbossChoppa said:

I think he made stacked single rank DDR5 8800 dimms that Micron has been teasing on their website for a bit.

I think that seems very likely - lines up with their 24 GB modules in their parts catalogue that are comprised of 8 3GB chips

[sub68]

1 hour ago, NastyFlytrap said:

Videos like these are really cool and the few remaining reasons why i even bother to watch LTT

I agree I mostly watch factory tour or intel extreme upgrade

[ImorallySourcedElectrons]

2 hours ago, ToboRobot said:

From an audio perspective, during factory tours with industrial background noise having background music as well is slightly distracting.  Either cut the music, or just re-record the voiceovers in post so we don't have the factory background noise.

They filtered out a lot of the background noise already I suspect, electronics cleanrooms are surprisingly noisy due to the air-conditioning.

 

3 hours ago, 05032-Mendicant-Bias said:

That was an enjoyable and informative video, it was a blast seeing those enormously expensive new machines. At the uni we saw decades old machines for I think 1um CMOS process.

You know that's done intentionally? The same equipment will happily do smaller feature sizes if you push it a little, the limitation is really the resolution at which you can make the mask and the wavelength of the light source (typically 365 nm for a mercury vapour lamp), but the added difficulties just aren't really worth it. Consider the fact that you're using this for research. The photolithography is typically contact lithography with an aligner, so the masks are consumable items by all intents and purposes, and the mask cost goes up quickly once you lose the ability to use the more typical photoplotters and LDI systems to make the contact masks. So it's not very attractive economically to do that in the first place. Add in the fact that once you go below 1 µm it becomes quite difficult to do optical inspection with conventional visible light microscopy, and you have researchers trying to stay above 1 µm if they can help it. Another reason for this is that silicon is transparent in infrared, so infrared microscopy is super duper useful for wafer inspection, and is limited even more by that nasty diffraction limit. Once you go past about 500-600 nm you got to resort to exotic microscopes, SEMs, TEMs, x-ray equipment, etc. Just not worth the hassle if you can avoid it. Another big issue is aligning the mask to the wafer if you're going down to these feature sizes, while doable through various tricks and methods, it ain't pleasant to do sub 200 nm error alignment on an old benchtop lithography machine (though many are mechanically stable enough to do it).

 

One thing I was a bit surprised about in this video is that they didn't do DBG (dice-before-grind) for this type of die stacking, I'd have expected chipping to be a serious concern.

[IceCaps97]

Hey look at that, I work at ASML on just a small part of that big EUV lithography machine that Linus mentioned. TSMC, Intel, Micron, etc. get all the attention cause they make the end products, but it's pretty neat finally hearing a shout-out to the supplier of the machines they all use. EUV is indeed as cool and complicated as Linus makes it out to be, and then some.

 

Really interesting video, these fab tours are some of the better content that LTT puts out and I'm all for giving more people a chance to see inside these places.

[ToboRobot]

27 minutes ago, ImorallySourcedElectrons said:

They filtered out a lot of the background noise already I suspect, electronics cleanrooms are surprisingly noisy due to the air-conditioning.

Filtered or not, it's there.  Seeing as it isn't really an interview on location due to NDA issues, thus my suggestion for dubbing the hosts voiceover for superior sound quality.

[BobVonBob]

3 hours ago, ToboRobot said:

Filtered or not, it's there.  Seeing as it isn't really an interview on location due to NDA issues, thus my suggestion for dubbing the hosts voiceover for superior sound quality.

I have the complete opposite view. Sure the sound quality might be better, but in my opinion the video/sound mismatch, sync issues, and loss of natural emotion that come with dubbing would be way more distracting and irritating than a little bit of background noise.

[NumLock21]

7 hours ago, ToboRobot said:

From an audio perspective, during factory tours with industrial background noise having background music as well is slightly distracting.  Either cut the music, or just re-record the voiceovers in post so we don't have the factory background noise.

That background noise is well over a billion dollars, and many of us would have never got the chance to the hear how they sound like, as they do their magic. It's nice the real noise is used, instead of some boring techno music.

[vsteel]

4 hours ago, ImorallySourcedElectrons said:

They filtered out a lot of the background noise already I suspect, electronics cleanrooms are surprisingly noisy due to the air-conditioning.

 

You know that's done intentionally? The same equipment will happily do smaller feature sizes if you push it a little, the limitation is really the resolution at which you can make the mask and the wavelength of the light source (typically 365 nm for a mercury vapour lamp), but the added difficulties just aren't really worth it. Consider the fact that you're using this for research. The photolithography is typically contact lithography with an aligner, so the masks are consumable items by all intents and purposes, and the mask cost goes up quickly once you lose the ability to use the more typical photoplotters and LDI systems to make the contact masks. So it's not very attractive economically to do that in the first place. Add in the fact that once you go below 1 µm it becomes quite difficult to do optical inspection with conventional visible light microscopy, and you have researchers trying to stay above 1 µm if they can help it. Another reason for this is that silicon is transparent in infrared, so infrared microscopy is super duper useful for wafer inspection, and is limited even more by that nasty diffraction limit. Once you go past about 500-600 nm you got to resort to exotic microscopes, SEMs, TEMs, x-ray equipment, etc. Just not worth the hassle if you can avoid it. Another big issue is aligning the mask to the wafer if you're going down to these feature sizes, while doable through various tricks and methods, it ain't pleasant to do sub 200 nm error alignment on an old benchtop lithography machine (though many are mechanically stable enough to do it).

 

One thing I was a bit surprised about in this video is that they didn't do DBG (dice-before-grind) for this type of die stacking, I'd have expected chipping to be a serious concern.

The universities get the old equipment that isn't use in manufacturing anymore, that is why they are older tools.

 

I think you are talking about other than 365nm (bench top, maybe G line for example) but in case you are going over I-line, 365nm is mercury lamps but they are not contact masks, or none I know of.  For example the ASML /100 /200 /400 machines are all 4:1 reduction lenses (I forget the Cannon model numbers).   The masks are only consumable in the fact that you need to have a new one if you need to make major changes.  Yes you can edit a mask but only minor corrections before it gets too messy for practical purposes. 

 

For I-line (365 nm process) the limit isn't the reticle but the wavelength of the light.  When you get spaces in the reticle at about the same distance as the wavelength of light you will get a scattering effect to the light.  That is where the larger the NA (numerical aperture) of the lens the more orders of light you can catch.  This is like catching the first few orders of light as in a Fourier approximation.   So if you have a square wave and get the first order of light you will get a sine wave but the more orders you collect the more and more close to the square wave.  There are phase shift reticles that can help get to smaller geometries but those get expensive quick.

 

 

You can then go into activation energy of the resist which will turn the example like the K=5 in to a square wave.  The activation energy smooths things out.  In the example above if the scale was 0 to 2 instead of -1 to 1, the resist wouldn't activate until energy was at .3 or so.   This lets the little squiggles either be seen as on or off to get back to that square wave. 

 

I won't go into all of the alignment and optical tricks done to make sure the pattern on the wafer is correct, because you have to keep in mine through all of the etching, stripping, adding films to the wafer, it will distort the wafer.   Bottom line it is easy to make a really tiny line, putting a contact on the end of it after the wafer has been through several process steps is the real trick.

 

Metrology you can go below 500nm optically, but like you said it does get harder.  You can see images around 250x optical and after that optical runs out of steam.  Much better to get into the SEM range.  TEM is normally used for much smaller geometries and xray is for things like packaged parts to see what is going on.  If you really need to see what is going on inside a part most of the time they will grind back the part and then break it where they want so they can get a good cross section. 

 

Much easier to grind the wafer down so the little diamond saw can slice the parts.  The actual saw has a very tiny blade and would have a really hard time going through that much wafer.  You could do it if you had too but it would take multiple passes.

 

 

 

[dogwitch]

i did enjoy the video very much.

[raf42]

One of the coolest LTT vids ever. The prior fab tours were amazing, but the fact that Linus got to literally build his own DIM? That's something out of my wildest dreams.

[shugen]

left: lttstore.com

right: ww.crucial.com

(yes, it miss a w

[ImorallySourcedElectrons]

4 hours ago, vsteel said:

The universities get the old equipment that isn't use in manufacturing anymore, that is why they are older tools.

Simply, no. Companies sell this equipment because it's still economically viable for many processes, we didn't get anything. Over the course of nearly a decade, the lab I worked in got exactly one ancient SEM from a company, that we had to go and pick up ourselves. However, we frequently bought new equipment meant for R&D, like the aforementioned aligners. Everything else we had to go on the second hand market and go bidding just like everyone else. This was especially painful for things like quartz tube furnaces when you couldn't go on location to inspect, and if the tube in the furnace is damaged it's pretty much worthless. So more often than not you bought damaged equipment that then had to be repaired. Keep in mind you're bidding against the guys who throw this equipment in a container and ship it to China and Taiwan.

 

4 hours ago, vsteel said:

I think you are talking about other than 365nm (bench top, maybe G line for example) but in case you are going over I-line, 365nm is mercury lamps but they are not contact masks, or none I know of.  For example the ASML /100 /200 /400 machines are all 4:1 reduction lenses (I forget the Cannon model numbers).   The masks are only consumable in the fact that you need to have a new one if you need to make major changes.  Yes you can edit a mask but only minor corrections before it gets too messy for practical purposes. 

Based on the "none I know of" and quickly resorting to ASML machines (instead of the much cheaper old Nikon aligners you find at many universities), I am going to assume you're one of the internet photolithography/cmos enthusiasts?

 

You must understand that technology R&D at university/laboratory level basic technology and CMOS node development are very different areas. In the latter you're challenging the dimensional aspects or optics in most cases, in the former you're challenging basic solid state physics. That's also why pretty much only a few labs in the world actually have the equipment to do CMOS scaling research, the one you've seen in this video is one of them. The only university research lab that I know of that has the equipment to still take part in the CMOS scaling race is imec - and that's heavily stretching the definition of university lab if you've ever been there.

 

How does this fit into the story you might ask? You have aligners and you have steppers. Steppers I'm going to assume you're familiarish with, but what aligners do is quite simple: you optically or mechanically align the mask with the wafer, you bring it in contact (not necessary but often recommended if you want good feature definition at the cost of some yield and mask lifetime) or you project through the mask. However, most modern aligners can do both (which is interesting for research purposes). This makes it so that aligners are simpler, easier to maintain, and way cheaper to run, making them very attractive for universities. Which isn't to say there's no use in having a stepper, it can be very valuable if you're running particular types of research (MEMS comes to mind), but usually it's just not very sensible from an economical point of view to run a stepper. Additionally, many folks mistake automated aligners for steppers since they look quite similar to an outsider, and many folks mix up reticle and mask as well.

 

But for R&D where you're not trying to challenge the realms of what's dimensionally possible you want an aligner for the following reasons:

• You're fighting solid state physics already, no need to fight optical limitations simultaneously if you can avoid it.
• NIR (Near infrared which is around +/- 1 µm wavelength) is incredibly useful for inspection inside the wafer, but this obviously limits you in terms of resolution. There are techniques to get around this but that's intricate, complicated, and a major headache.
• Masks are incredibly cheap for aligners, it's just a 1:1 copy of your design that was made using a photoplotter or DWL system on a regular glass plate with a chrome layer. No need to waste valuable e-beam time, and no need to run fancy software to generate a mask from your design - all you need is something along the lines of Tanner or CleWin that can output GDS or CIF.
• You can fit multiple designs on a single mask and put all of them on a wafer at once, with a stepper you'll often have to switch reticle and use separate wafers to do this.
• You're not limited by the maximum reticle size, so you can fan-out and make as many test structures as you want.
• Aligners tend to use mercury vapour/arc lamps without any real filter (though often you can introduce one to be more selective), meaning you can expose most resists. This also allows you to use soda-lime float glass as mask, since it's still somewhat transparent at 365 nm, if you go further you have to switch to quartz (which breaks the bank very quickly).
• You're not dealing with optical effects, what you have on your mask is transferred to the photoresist, plain and simple.
• Aligners can also do imprinting and embossing, making them very useful for silicon photonics applications where you're making gratings, etc.

Companies like MicroTec and EVG still very much make aligners for R&D purposes and small scale production runs in RF, silicon photonics and power electronics.

8 hours ago, vsteel said:

The masks are only consumable in the fact that you need to have a new one if you need to make major changes. 

No, aligner masks have a limited life, you bring the mask in contact with the photoresist in many instances. You can only clean them so many times before there are defects in the chrome layer, you also have to deal with defects due to particles in many instances.

8 hours ago, vsteel said:

Yes you can edit a mask but only minor corrections before it gets too messy for practical purposes. 

Again, "minor corrections" is another reason why we did not use steppers and reticles as you describe, reticles take time to make and are expensive, 1:1 soda-lime masks are quick and cheap. Additionally, modifying a 1:1 contact mask for 1 µm is easy. I've literally scratched out parts of the chromium layer using a stereo microscope, a plastic skewer or scalpel, and a steady hand. But if you want to be more precise and have something like a DWL system: Shadow mask desired area you wish to restructure, put on a new chromium or aluminium layer, strip photoresist, apply new photoresist, cover/flood expose area outside the area you wish to edit, use a direct write system to write the new design on that area of the mask, etch, strip resist, inspect. Quite nice for quick turn-around if you don't want to wait a week for the mask to arrive. Making modifications like that on a reticle ain't pleasant, if at all possible.

 

8 hours ago, vsteel said:

For I-line (365 nm process) the limit isn't the reticle but the wavelength of the light.  When you get spaces in the reticle at about the same distance as the wavelength of light you will get a scattering effect to the light.  That is where the larger the NA (numerical aperture) of the lens the more orders of light you can catch.  This is like catching the first few orders of light as in a Fourier approximation.   So if you have a square wave and get the first order of light you will get a sine wave but the more orders you collect the more and more close to the square wave.  There are phase shift reticles that can help get to smaller geometries but those get expensive quick.

Joke's on you, contact aligners do not use a lens like that, the wavelength of light is in fact the limiting factor with them. While they're a bit more complicated, what you literally have is your wafer with photoresist, the mask is put directly on top with the metal (almost) touching the photoresist, and a mercury lamp (or UV LEDs in modern cheaper equipment) sitting relatively far away shining light through the mask. The reason why you go for 365 nm is because you can use cheap soda-lime glass masks, while the lamps in principle should output enough power to do something practical at 312 nm and 254 nm as well. In any case, if your features approach the wavelength of the lamp you're using, you're going to have bad time. In principle it can be done, but it's really not recommended - read papers from the 70s and 80s if you must know why this approach was quickly abandoned. But at that point it's easier to just toss your wafer into the e-beam machine and directly expose it like that. There's no point in making expensive reticles if you're going to make changes each iteration - like you're likely to do in research.

 

8 hours ago, vsteel said:

I won't go into all of the alignment and optical tricks done to make sure the pattern on the wafer is correct, because you have to keep in mine through all of the etching, stripping, adding films to the wafer, it will distort the wafer.   Bottom line it is easy to make a really tiny line, putting a contact on the end of it after the wafer has been through several process steps is the real trick.

And this is one of the reasons why the feature size is kept above 1 µm at laboratory scale, because then you can just use the optical microscope built into most aligners to align everything sufficiently precise using standard alignment marks. Some steppers use quite exotic systems for alignment.

 

8 hours ago, vsteel said:

Metrology you can go below 500nm optically, but like you said it does get harder.  You can see images around 250x optical and after that optical runs out of steam.  Much better to get into the SEM range.  TEM is normally used for much smaller geometries and xray is for things like packaged parts to see what is going on.  If you really need to see what is going on inside a part most of the time they will grind back the part and then break it where they want so they can get a good cross section. 

By limiting yourself in resolution you can significantly simplify the inspection of what you made, I cannot stress this enough. It's really valuable to be able to throw your wafer underneath a wafer inspection microscope during your process to see if things are going right. And having to use immersion objectives and other solutions really cuts into your time a lot. Additionally, it's really valuable to have a three-dimensional view where you do not have to account for optical effects to interpret what you're seeing, and most of the alternative techniques only provide false 3D or cannot guarantee that what you see is what's actually there. This is why you stay above 1 µm. Additionally, most cameras in wafer inspection microscopes are sensitive to near infrared, so when you remove the filter from the light source you can quickly inspect for defects inside the silicon after doing something like etching a deep trench.

 

And you must understand, SEMs are often not very practical for in-production inspection. You often have to deposit gold or carbon on top of your wafer, and that's assuming your SEM can fit a wafer at all (usually the tilt system is a significant limiting factor), it's also a really bad idea to use a SEM with some categories of charge-sensitive devices. TEMs are pretty much exclusively used in post-mortem examination and require you to destroy your sample anyhow. (It also generally involves a lot of cursing with FIBs or ion-beam polishers.) And X-Ray is a lot more useful than you think it is, while I agree its use in production is limited, in research it's extremely valuable because it can detect crystallographic defects introduced by doping and thermal steps. Micro-CT also has plenty of space before you even get to packaging, especially for MEMS and damascene processes.

8 hours ago, vsteel said:

Much easier to grind the wafer down so the little diamond saw can slice the parts.  The actual saw has a very tiny blade and would have a really hard time going through that much wafer.  You could do it if you had too but it would take multiple passes.

And this part is what made me really think you're an internet enthusiast. Dice-before-grind is a technique where you score the wafer with a dicing machine, and then you singulate the dies by grinding and polishing away the backside. This avoids the chipping you normally get at the bottom edge of the dies in the dicing streets and significantly reduces the mechanical forces the dies experience, it allows you to go much thinner by reducing the thermal sensitivity of the dies and makes for nicer side-walls. Disco shows this reasonably well I think: https://www.disco.co.jp/eg/solution/library/dbg/dbg_process.html

 

 

[ToboRobot]

9 hours ago, BobVonBob said:

I have the complete opposite view. Sure the sound quality might be better, but in my opinion the video/sound mismatch, sync issues, and loss of natural emotion that come with dubbing would be way more distracting and irritating than a little bit of background noise.

Dubbing is very common, you don't notice if it is done right.

[IanSzot]

I've seen some people on the video comments saying the 24GB module is groundbreaking, can someone explain why that is? A comment said that we're steering away from "binary ram modules", like 1->2->4->8->16 and so on and going for "non binary memory", I did some googling and didn't find much information on this topic other than this: https://www.servethehome.com/sk-hynix-shows-non-binary-ddr5-capacities-at-intel-innovation-2022/

 

but it doesn't explain what's so special about it and what are the benefits

[ImorallySourcedElectrons]

28 minutes ago, IanSzot said:

I've seen some people on the video comments saying the 24GB module is groundbreaking, can someone explain why that is? A comment said that we're steering away from "binary ram modules", like 1->2->4->8->16 and so on and going for "non binary memory", I did some googling and didn't find much information on this topic other than this: https://www.servethehome.com/sk-hynix-shows-non-binary-ddr5-capacities-at-intel-innovation-2022/

 

but it doesn't explain what's so special about it and what are the benefits

Wouldn't be surprised if they were somehow taking 64 GB modules where a chip failed and marking them as 48 GB to sell them anyway.

[Zodiark1593]

An interesting way to sneak in a teaser at the end, pretty much letting Linus stumble right into it. I like this company.

[vsteel]

3 hours ago, ImorallySourcedElectrons said:

Simply, no. Companies sell this equipment because it's still economically viable for many processes, we didn't get anything.

My company will give things to universities because it helps with the partnership and it also is a tax write off so they still get the benefit like they sold it. 

 

3 hours ago, ImorallySourcedElectrons said:

Based on the "none I know of" and quickly resorting to ASML machines (instead of the much cheaper old Nikon aligners you find at many universities), I am going to assume you're one of the internet photolithography/cmos enthusiasts?

Nope, I have worked on ASML steppers to step and scan systems all the way to twin scan machines.   I didn't work on the Cannons personally and I never was around any of the Nikon systems.  I have over a decade of fab experience in a manufacturing setting.  I was a tool owner over a fab for a while as well before I changed roles in my company. 

 

3 hours ago, ImorallySourcedElectrons said:

 

You must understand that technology R&D at university/laboratory level basic technology and CMOS node development are very different areas.

I see the misunderstanding.  You and I are at different ends of the spectrum.  For R&D or manufacturing in a major semiconductor company no one has used a contact mask for decades maybe a mom and pop shop might. 

 

3 hours ago, ImorallySourcedElectrons said:

And you must understand, SEMs are often not very practical for in-production inspection. You often have to deposit gold or carbon on top of your wafer, and that's assuming your SEM can fit a wafer at all (usually the tilt system is a significant limiting factor), it's also a really bad idea to use a SEM with some categories of charge-sensitive devices. TEMs are pretty much exclusively used in post-mortem examination and require you to destroy your sample anyhow. (It also generally involves a lot of cursing with FIBs or ion-beam polishers.) And X-Ray is a lot more useful than you think it is, while I agree its use in production is limited, in research it's extremely valuable because it can detect crystallographic defects introduced by doping and thermal steps. Micro-CT also has plenty of space before you even get to packaging, especially for MEMS and damascene processes.

Not true, SEMs are used in manufacturing all of the time and nothing needs to be deposited on the wafer.  They are part of the line monitoring in a fab, they are running non stop checking the line for issues.  There are ways around the charging issue.  Keep in mind I am talking from a semiconductor manufacturing perspective so we might be running better equipment than you probably are.

 

3 hours ago, ImorallySourcedElectrons said:

And this part is what made me really think you're an internet enthusiast. Dice-before-grind is a technique where you score the wafer with a dicing machine, and then you singulate the dies by grinding and polishing away the backside. This avoids the chipping you normally get at the bottom edge of the dies in the dicing streets and significantly reduces the mechanical forces the dies experience, it allows you to go much thinner by reducing the thermal sensitivity of the dies and makes for nicer side-walls. Disco shows this reasonably well I think: https://www.disco.co.jp/eg/solution/library/dbg/dbg_process.html

Don't have a need to do it that way.  We are not having chipping issues doing the grind then dice.   Manufacturers don't always have the best processes and recipes, they generally have the easiest, you need to develop your own process to be as efficient as you can.   When manufacturing wafers, every second counts so whatever you can do to shave off time is worth it. 

 

No internet enthusiast here, over 25 years of semiconductor experience, front end to back end with lots of stops in the middle.  I am still in the business today. 

 

 

[ImorallySourcedElectrons]

10 minutes ago, vsteel said:

My company will give things to universities because it helps with the partnership and it also is a tax write off so they still get the benefit like they sold it. 

Nice, I doubt it'd work as a tax write off over here, the only thing they seem to care about is getting rid of it as cheaply as humanly possible.

 

10 minutes ago, vsteel said:

Nope, I have worked on ASML steppers to step and scan systems all the way to twin scan machines.   I didn't work on the Cannons personally and I never was around any of the Nikon systems.  I have over a decade of fab experience in a manufacturing setting.  I was a tool owner over a fab for a while as well before I changed roles in my company. 

Might be geographically divided, I've rarely seen Cannon machines around here, but I've had the displeasure of operating Nikon machines at multiple occasions. Semi-recent ASML equipment is unobtainium at auction or from refurbishers.

 

11 minutes ago, vsteel said:

I see the misunderstanding.  You and I are at different ends of the spectrum.  For R&D or manufacturing in a major semiconductor company no one has used a contact mask for decades maybe a mom and pop shop might. 

I know that one fairly sizable Taiwanese manufacturer of power devices was still using aligners for their lower volume 6" production in 2016, though primarily in projection mode I'd imagine. Most likely because they're not running into reticle size limitations that way, which is probably a consideration when making things like thyristors, and you're not exactly chasing process nodes in those sort of applications. And the type of R&D is indeed very different at universities, you're talking about taking a known concept and moving it into production most likely, I'm talking about the stage of "mhhh, that's funny" to figuring out how to make something that repeats that behaviour consistently. 

 

And overall, for universities it's really an economics operation. Consider the cost of operating a stepper, usually you need to keep the machine on for extended periods of time, a surprising amount of them use various technical gasses in a small and steady continuous flow, cooling water for the light source, maintenance, etc. So I just don't see how you can run a machine like that for less than €20k to €50k a year. Meanwhile, that aligner costs maybe €50 in power and €200 in maintenance a year to run. And that's not even considering the price of a reticle, meanwhile a mask for that aligner will set you back €250-400, or even less if you're willing to wait for a couple of weeks. It just doesn't make much sense for a university lab to purchase a stepper unless if they're able to run tens to hundreds of wafers through it on a daily basis. If you get one for free the economics change slightly of course, so I wonder how often the ones your company gave away are actually used.

 

15 minutes ago, vsteel said:

Not true, SEMs are used in manufacturing all of the time and nothing needs to be deposited on the wafer.  They are part of the line monitoring in a fab, they are running non stop checking the line for issues.  There are ways around the charging issue.  Keep in mind I am talking from a semiconductor manufacturing perspective so we might be running better equipment than you probably are.

I think you're running the equipment with a different goal, you're going to be running lower voltages and less current since you're probably not trying to run something like an EDS, etc. There would be little use for that in production, meanwhile in R&D you got to assume that your idiotic colleague contaminated crucibles or dipped a dirty pipette straight into the photoresist stock solution, leading to odd intermetalics that completely ruin the bumps you're trying to grow on the chip bond pads, etc. And there are indeed other ways to prevent the charge build-up, including the completely bonkers alpha emitter sources, but I think the bigger question is what you're looking at, which quality you need, and at which point in your process. Additionally, in production you have airlocks on your equipment, which is very much missing in R&D. So all the high vacuum approaches are off the table for us, which eliminates several techniques to get around these issues. So what's standard for you would not work very well in a lab setting.

 

36 minutes ago, vsteel said:

Don't have a need to do it that way.  We are not having chipping issues doing the grind then dice.   Manufacturers don't always have the best processes and recipes, they generally have the easiest, you need to develop your own process to be as efficient as you can.   When manufacturing wafers, every second counts so whatever you can do to shave off time is worth it. 

That's why DBG is quite nice, it doesn't really take extra time or money. Though I'm a bit surprised you guys run it yourself, it's hard to beat Disco's pricing at this point.

[vsteel]

26 minutes ago, ImorallySourcedElectrons said:

I know that one fairly sizable Taiwanese manufacturer of power devices was still using aligners for their lower volume 6" production in 2016, though primarily in projection mode I'd imagine. Most likely because they're not running into reticle size limitations that way, which is probably a consideration when making things like thyristors, and you're not exactly chasing process nodes in those sort of applications. And the type of R&D is indeed very different at universities, you're talking about taking a known concept and moving it into production most likely, I'm talking about the stage of "mhhh, that's funny" to figuring out how to make something that repeats that behaviour consistently. 

Yea, running something like thyristors or basic logic or power circuits you lose more wafer to the saw than you do useful silicon.   The company I am at was 8 inch only back in the mid 90s, and we converted from 8 inch to 12 inch many years ago.  We do run some pretty odd things and while most are a known concept, there are branches of R&D which are looking into the "could this possibly work or be made repeatable".  We partner with other companies and universities for that kind of work.

 

26 minutes ago, ImorallySourcedElectrons said:

And overall, for universities it's really an economics operation. Consider the cost of operating a stepper, usually you need to keep the machine on for extended periods of time, a surprising amount of them use various technical gasses in a small and steady continuous flow, cooling water for the light source, maintenance, etc. So I just don't see how you can run a machine like that for less than €20k to €50k a year. Meanwhile, that aligner costs maybe €50 in power and €200 in maintenance a year to run. And that's not even considering the price of a reticle, meanwhile a mask for that aligner will set you back €250-400, or even less if you're willing to wait for a couple of weeks. It just doesn't make much sense for a university lab to purchase a stepper unless if they're able to run tens to hundreds of wafers through it on a daily basis. If you get one for free the economics change slightly of course, so I wonder how often the ones your company gave away are actually used.

I can see your predicament, for major semiconductor operations 50K would be in the noise of things and that scanner is running 24x7 on other things as well. 

 

26 minutes ago, ImorallySourcedElectrons said:

 

I think you're running the equipment with a different goal, you're going to be running lower voltages and less current since you're probably not trying to run something like an EDS, etc. There would be little use for that in production, meanwhile in R&D you got to assume that your idiotic colleague contaminated crucibles or dipped a dirty pipette straight into the photoresist stock solution, leading to odd intermetalics that completely ruin the bumps you're trying to grow on the chip bond pads, etc. And there are indeed other ways to prevent the charge build-up, including the completely bonkers alpha emitter sources, but I think the bigger question is what you're looking at, which quality you need, and at which point in your process. Additionally, in production you have airlocks on your equipment, which is very much missing in R&D. So all the high vacuum approaches are off the table for us, which eliminates several techniques to get around these issues. So what's standard for you would not work very well in a lab setting.

 

We are high vacuum, we get photo resist spun on by a track, straight from the bottle and filtered with verified particle counts to qual the bottle.  No manual processing so we take the human element out of it.  All processing happens in a machine chamber, no idiotic colleague issues here for the most part.  Always told new people, always keep resist out of the diffusion furnace and metal out of the piranha tank and you will be OK.