zen 3 Upgrades people, Upgrades- Zen 3 has finished its design and coming 2020?

[Taf the Ghost]

14 minutes ago, Trixanity said:

While the name could be arbitrary for all intents and purposes, AMD seems to consider bumping the numbers to be part of architectural improvements. Zen+ had none hence the difference. Of course there's plenty room to backpedal on it. 

It tends to get lost that Zen+ was mostly just a microcode changes. Most of the changes actually landed on TR1 and first-gen Epyc, with the last being the cache improvements that showed up as Zen+.

 

It also only happened because 7nm was actually pretty late. AMD had hoped to move from Zen1 to Zen2 by late last year, rather than launch a Zen+ cycle. With TSMC's current pace, AMD can do 12-15 month release cycles. (There's an argument they pushed Zen2 back a few months because they wanted space for Zen3 to land in late 2020.)

[leadeater]

3 minutes ago, Taf the Ghost said:

It tends to get lost that Zen+ was mostly just a microcode changes. Most of the changes actually landed on TR1 and first-gen Epyc, with the last being the cache improvements that showed up as Zen+.

Yep, but as far as naming goes there are no rules around it and AMD could have used Zen 2, an improvement is an improvement after all and a name is just a name. We joke about ++++ on Intel side but those are more unofficial or fab node designations, they actually name each architecture even if the changes are small, even Haswell Refresh is officially Devil's Canyon.

 

Doesn't mean AMD has to do similar but it also doesn't mean a refresh has to use a + denotation either.

[Taf the Ghost]

16 minutes ago, leadeater said:

Yep, but as far as naming goes there are no rules around it and AMD could have used Zen 2, an improvement is an improvement after all and a name is just a name. We joke about ++++ on Intel side but those are more unofficial or fab node designations, they actually name each architecture even if the changes are small, even Haswell Refresh is officially Devil's Canyon.

 

Doesn't mean AMD has to do similar but it also doesn't mean a refresh has to use a + denotation either.

It gets a little confusing when the only place AMD uses the terms is actually in PR. Each project has an internal codename. Zen1's core design was Zeppelin. Zen2's is Valhalla. The Server CPUs are named after Italian cities (did you know AMD sponsors Ferrari? lol). Desktop design is going from Ridges to Painters. Thus Matisse and Renoir this generation, along with Vermeer, Dali and Van Gogh next generation. 

 

TR parts are a little strange. They seem to be location names that seem like parks in CA.

[AkatsukiKun]

15 hours ago, realpetertdm said:

If Zen 4 is actually 6nm then is AMD going to stick with TSMC & GlobFoundries or will they consider other companies?

 

Also I wonder why they don't use samsung's process

https://www.anandtech.com/show/13277/globalfoundries-stops-all-7nm-development 

If you give a quick rundown they're stopping or at least pausing 7nm class development because it's just not worth the investment to be on the bleeding edge of semiconductors, mind you the article was written august of last year, it's unlikely things have changed, but Zen is most likely going to be with Global Foundries or Samsung (or x-nm licensed by GF).

[AkatsukiKun]

7 hours ago, Taf the Ghost said:

It gets a little confusing when the only place AMD uses the terms is actually in PR. Each project has an internal codename. Zen1's core design was Zeppelin. Zen2's is Valhalla. The Server CPUs are named after Italian cities (did you know AMD sponsors Ferrari? lol). Desktop design is going from Ridges to Painters. Thus Matisse and Renoir this generation, along with Vermeer, Dali and Van Gogh next generation. 

 

TR parts are a little strange. They seem to be location names that seem like parks in CA.

AMD used to sponsor F1 cars that are related to Ferrari, though I don't know how well their sponsorships are right now since their finances are doing better now.

[Taf the Ghost]

1 minute ago, AkatsukiKun said:

AMD used to sponsor F1 cars that are related to Ferrari, though I don't know how well their sponsorships are right now since their finances are doing better now.

https://formula1.ferrari.com/en/partners/amd/

 

AMD's GPUs are the best in Catia, which just happens to be one of the favored programs by F1 teams. lol

[imreloadin]

Can't wait for everyone to jump on the bandwagon of "leaks" started by Adored and everyone claiming that Zen 3 will definitely "hit 5GHz on air" or some other bullshit like that

[Kisai]

11 hours ago, cj09beira said:

isn't 6nm 7nm+ with more euv layers?, i wander what they will do, they might try to avoid quadpaterning but at the same time the features should be large enough to where its not much of a issue but if the euv 7nm is cheaper as it was rumored then thats what they will use 

i dont see quad channel coming to consumer market anytime soon, instead by then we should have multi GigaBytes of cache using something akin to hbm

 

The reason we never see 4-channel/6-channel memory controllers in the consumer end is that it would bleed the high-end market (servers, workstations, etc) for the CPU's. Just like for some strange reason we never get 64-lanes available to the PCIe slots (for 4x GPU's, or 3X GPU's and 4 NVme drives) , we always get just 24 lanes so that you can never make use of two GPU's at their full capacity. If you want SLI, pay the extra $$$$ for the workstation.

 

Ever wonder why Apple was always just content to use the workstation Xeons in the Mac Pro but never released a single desktop-class CPU in any other product? That's why. If you want the expansion capability, you pay the much higher premium for the Pro product.

[mr moose]

5 hours ago, Tedny said:

AMD said AM4 is until 2020, so we are getting 3 gens on one socket with AMD or 4 gens on the same socket with 2 refreshes... So, Isn't AMD market itself like more customer-friendly, so 4 gens will be better for AMD marketing strategy 

If we getting Zen3 in 2020, what it make Zen2 than, Filler or Ryzen 3 is just byproduct or leftover of Epyc CPU's? 

 

The number of generations you'll be able to run on AM4 will be at least 4 (my humble guess), but where it stops is only in the hands of feature updates, AMD and physical limitations.    From memory the previous longest duration a platform supported was 6 years, however over that 6 years there were breaks in compatibility for certain features, so whilst we might get Ryzen 3rd gen on AM4 as we own now, there is no guarantee we will be able to use all of the features in that CPU.

 

So long story short, AM4 is more versatile if you are happy with compromises (which is great for some customers),  However how much of a benefit that is to AMD will depend on how well Intel perform over the next few years.    The advantage AMD had with AM2/3 was lost to better performance from Intel processors.  The advantage AMD is enjoying now is better processors not really the promise of platform longevity. 

[porina]

Random thought: I'd imagine the next major platform change will be to support DDR5, maybe they call it AM5. However, with the chiplet design philosophy, could they have two versions of the IOD, one with DDR5 support, and the existing one with DDR4 support (or future revision thereof). Could Zen 3 support both? If not Zen 3, same question for Zen 4... basically, would they offer an overlap generation?

[Taf the Ghost]

2 minutes ago, porina said:

Random thought: I'd imagine the next major platform change will be to support DDR5, maybe they call it AM5. However, with the chiplet design philosophy, could they have two versions of the IOD, one with DDR5 support, and the existing one with DDR4 support (or future revision thereof). Could Zen 3 support both? If not Zen 3, same question for Zen 4... basically, would they offer an overlap generation?

The PHY for DDR controllers can handle both 4 and 5 in the same silicon, so it'd only be a matter of packages. AM4 & SP3 don't have enough pins to run DDR5. As a result, we very well could see AMD roll out split generations. They're supporting SP3 through Milan (Zen3) and AM4 through 2020 (doesn't mean desktop, assuredly), which lines up with splitting things out if AMD sees the market utility. 

 

I suspect that the next IOD will have the dual DDR4/5 controllers, and then AMD will decide fairly late whether to run out with new platforms and Zen3 parts. Zen4 will transition to DDR5 for sure.

 

The segment to look for this would be rumblings around 24c Desktop parts. Those would be the ones that DDR5 would be required for. Dual channel DDR4 is going to bottleneck those hard under any load. AMD would end up rolling out the AM5 socket for a small number of "HEDT on Desktop" parts to get the ecosystem rolling.

[mr moose]

41 minutes ago, Taf the Ghost said:

The PHY for DDR controllers can handle both 4 and 5 in the same silicon, so it'd only be a matter of packages. AM4 & SP3 don't have enough pins to run DDR5. As a result, we very well could see AMD roll out split generations. They're supporting SP3 through Milan (Zen3) and AM4 through 2020 (doesn't mean desktop, assuredly), which lines up with splitting things out if AMD sees the market utility. 

 

I suspect that the next IOD will have the dual DDR4/5 controllers, and then AMD will decide fairly late whether to run out with new platforms and Zen3 parts. Zen4 will transition to DDR5 for sure.

 

The segment to look for this would be rumblings around 24c Desktop parts. Those would be the ones that DDR5 would be required for. Dual channel DDR4 is going to bottleneck those hard under any load. AMD would end up rolling out the AM5 socket for a small number of "HEDT on Desktop" parts to get the ecosystem rolling.

DDR5 being claimed a 2020 release allows AMD to jump to a new platform without breaking promises, although I can see them designing AM4+ so DDR5 works but older AM4 will be restricted to the mobo's DDR4 limitation.    

 

I can't see 24c as a consumer thing for another 2-3 years yet at least.  Only because majority consumers don't need it therefore it is not really a viable market. Therefore when they hit the market and are viable,  most people will already have or be ready to upgrade to a DDR5 platform.  

[Drak3]

1 hour ago, Kisai said:

we always get just 24 lanes so that you can never make use of two GPU's at their full capacity. If you want SLI, pay the extra $$$$ for the workstation.

Unless you're running 1080Ti equivalents or better, you're not even saturating PCIe 3.0 x8 in most cases. And if you are running those, you're seeing slight bottlenecking in some games.

[Akira Shimazu]

AMD is really pushing hard right? im really curious about Zen 3

[Humbug]

22 hours ago, SlimyPython said:

That means we can expect higher clock speeds paired with lower power consumption. 

Do we have any reliable sources claiming that 7nm EUV will enable further clockspeeds jumps?

I thought that going forward it's gonna be a battle just to maintain current clockspeeds.

[leadeater]

19 hours ago, Humbug said:

Do we have any reliable sources claiming that 7nm EUV will enable further clockspeeds jumps?

I thought that going forward it's gonna be a battle just to maintain current clockspeeds.

It's possible as one of the technical improvements of EUV is the traces can be much more defined and accurate so should be able to sustain more power, lower resistance and less losses overall. Picture a line drawn with a wide tip pencil with little downward pressure compared to a fine tip pencil with slightly more downward pressure, the fine tip produces a superior line with a higher degree of accuracy for the width of the line.

 

 

However the upper clock limits may not change, because you need to pair architectural changes to support it, but variance in overall die quality and per core quality should reduce meaning lower voltages required for given clocks and more cores in total being able to achieve higher clocks, as such lower heat and power draw.

 

My prediction for 7nm EUV Zen CPUs without significant architecture improvements would be sustained 4.6Ghz single core or 2 core boost with a dynamic all core boost in the 4.3Ghz-4.4Ghz range (currently 4.1Ghz) under the highest demand workloads.

[pizapower]

7 hours ago, imreloadin said:

Can't wait for everyone to jump on the bandwagon of "leaks" started by Adored and everyone claiming that Zen 3 will definitely "hit 5GHz on air" or some other bullshit like that

8 or 12 core Zen 3 for $99

[Taf the Ghost]

3 hours ago, Humbug said:

Do we have any reliable sources claiming that 7nm EUV will enable further clockspeeds jumps?

I thought that going forward it's gonna be a battle just to maintain current clockspeeds.

We're going to see clock regressions generally speaking going forward, though architecture does matter. Will matter less if some of the other rumors going around pan out.

[Humbug]

14 minutes ago, Taf the Ghost said:

We're going to see clock regressions generally speaking going forward, though architecture does matter. Will matter less if some of the other rumors going around pan out.

I guess Intel's 10nm shows that clearly. We may someday get to a point where we are forced to use slightly older nodes for the highest most expensive performance parts. 

 

Yep final clockspeed is always a function of architecture and process, both matter. For example moving from 14nm to 7nm created bigger percentage clock speed jumps for GCN GPUs than it did for ryzen CPUs.

[GoldenLag]

9 hours ago, mr moose said:

DDR5 being claimed a 2020 release allows AMD to jump to a new platform without breaking promises, although I can see them designing AM4+ so DDR5 works but older AM4 will be restricted to the mobo's DDR4 limitation.    

I see them waiting a year to use DDR5 and pair it with Zen 4 (or Zen 5 because AMD shure loves to work with numbers, like Zen 5 on Am5 with DDR5 fabricated on 5nm)

 

They still have enough bandwidth on DDR4 and higher memmory speeds to help IF seems to be limited to IF not being able to clock higher. 

[mr moose]

1 minute ago, GoldenLag said:

I see them waiting a year to use DDR5 and pair it with Zen 4 (or Zen 5 because AMD shure loves to work with numbers, like Zen 5 on Am5 with DDR5 fabricated on 5nm)

 

They still have enough bandwidth on DDR4 and higher memmory speeds to help IF seems to be limited to IF not being able to clock higher. 

No.5 is alive.   

[Taf the Ghost]

1 hour ago, Humbug said:

I guess Intel's 10nm shows that clearly. We may someday get to a point where we are forced to use slightly older nodes for the highest most expensive performance parts. 

 

Yep final clockspeed is always a function of architecture and process, both matter. For example moving from 14nm to 7nm created bigger percentage clock speed jumps for GCN GPUs than it did for ryzen CPUs.

It's probably best to characterize a node by the different type of general clocks it allows. There's definitely "GPU-Class" clocks and "CPU-class" clocks. Plus other types of devices on a node run in generally the same realm. Intel's nodes are good CPU-class but really bad GPU-class, for whatever reason. TSMC's HPC nodes appear to be better GPU-class than CPU-Class, but CPU-class is still quite good.

 

The other thing, and this is that rumor, but there's approaches to making pseudo-core solutions for Single Core Performance. While it'll sound strange, Bulldozer (and the Orochi concept in general) wasn't actually wrong. It was simply too early and some of the details were just not ready. AMD isn't going back to CMT, but the design concept works if done properly. We've already seen the first hint at this in Navi. Navi has 40 CUs, but it's really a 20 Dual-CU design. 2 CUs can operate at one, for the types of workloads that simply don't get the benefit from separating the operations. I've taken to calling it a "fusible front-end" for Zen3, but this is deep in the rumor mill and incredibly hazy. We'll know more when some patent filings drop next year, but AMD has something up their sleeve for Single Core Performance and that's one of the ways to do it. So the reality is that there are ways to simply keep stacking pseudo-cores on top of each other to act like one to the OS. That's where some of this stuff is heading.

 

Other thing is fixed-function units are going to get common. Not sure exactly what functions AMD will choose (they already do AES acceleration this way), but that'll also be very common going forward. Clocks were nice & easy, but there's still a long ways before we hit performance walls.

[leadeater]

18 minutes ago, mr moose said:

No.5 is alive.   

You managed to find a Short Circuit?

[Taf the Ghost]

21 minutes ago, GoldenLag said:

I see them waiting a year to use DDR5 and pair it with Zen 4 (or Zen 5 because AMD shure loves to work with numbers, like Zen 5 on Am5 with DDR5 fabricated on 5nm)

 

They still have enough bandwidth on DDR4 and higher memmory speeds to help IF seems to be limited to IF not being able to clock higher. 

Zen5 is on 5nm+. The node should volume ramp in 2021. Zen4 Epycs will definitely be DDR5 (Intel has announced they'll be on DDR5 in 2022 already), Desktop is down to other factors, I would assume. We could see desktop DDR5 anywhere from Zen3 through Zen5.

[mr moose]

7 minutes ago, leadeater said:

You managed to find a Short Circuit?

It came to me like a bolt of lightening.