Silicon Lottery Announces Ryzen 3000 Bins

[cj09beira]

its really interesting that they have their max vcore so low, 1.25 is their top bin so clocks could increase quite a bit just by allowing more voltage, i wonder where they got that voltage, i think someone from amd talked about 1.3 + something, maybe they went from better safe than sorry

sent them a message asking if there is a particular reason as to why its 1.25v

[optimuss]

17 minutes ago, Anomnomnomaly said:

Are people REALLY that dumb, that paying that much is a good idea. Base price is $500 and I've not seen one that can't do 4ghz all core in all of the reviews I've seen.  So paying an extra $309.99 for a sure fire 200mhz has to be the definition of moronic.

If you build e.g. a 3-4k $ pc does it really matter that much? I wouldn't buy this chip but I bought 7820x from SL and it was worth it to me (4.9 GHz bin).

[Suika]

9 hours ago, Jurrunio said:

thing is 5GHz is already easy to achieve as long as you dont use bad boards or coolers. dont need binning at that point

Not every consumer is able to figure out an overclock but still wants the performance of an overclock. My friend is one of those people so I understand the desire for a service like that of Silicon Lottery.

 

Also not every processor can hit 5GHz, you can check the products on SL's website to see what percentage of chips hit the frequencies at their recommended settings. In the case of the 9700k, 89% of chips hit 5GHz and the pricing reflects that. Similarly, only 10% of chips can hit 5.2GHz, so those chips sell at a premium.

9 hours ago, Jurrunio said:

delid... soldered CPUs?

I believe they still offer the service for Coffee Lake refresh, as there still is a benefit to delidding it, despite being soldered. 

[ravenshrike]

The only use case I can see for these chips is if you want high all core overclocks in a SFF build.

[Dabombinable]

8 hours ago, porina said:

 

The difference there though was far less, and only the IHS got lapped:

 

[Dabombinable]

-snip- it did nothing after I hit reply the first time...
 

 

[mr moose]

3 hours ago, Dabombinable said:

-snip- it did nothing after I hit reply the first time...
 

 

That happens to me a lot, now when it does that I open a new tab and check the thread to see if it posted before hitting it again.

[Nowak]

23 hours ago, Drak3 said:

But they're supposed to be 5GHz capable parts!!1!!!!!!

 

 

/s

I am pretty sure the only reason why the Adored "leak" kept getting passed around was because it was what everyone wanted.

 

I have a 5GHz capable 8086K and I don't even want to go beyond 4.9GHz

[thorhammerz]

Seems like there's several different things that are being conflated?

 

> Zen 2 (the architecture)

> Zen 2 (the CPU cores as a standalone unit / chiplet / whatever)
> Zen 2 (the CPUs package, e.g. what Amazon delivers to your door)
> 7nm Silicon (what TSMC is selling)

[Drak3]

1 minute ago, thorhammerz said:

Seems like there's several different things that are being conflated?

 

> Zen 2 (the architecture)

> Zen 2 (the CPU cores as a standalone unit / chiplet / whatever)
> Zen 2 (the CPUs package, e.g. what Amazon delivers to your door)
> 7nm Silicon (what TSMC is selling)

There really isn't. Zen 2 is the architecture of Ryzen 3000, and Ryzen 3000 is the product range of the Zen 2 architecture. Unless we get a refresh, they're functionally interchangeable.

[thorhammerz]

2 minutes ago, Drak3 said:

There really isn't. Zen 2 is the architecture of Ryzen 3000, and Ryzen 3000 is the product range of the Zen 2 architecture. Unless we get a refresh, they're functionally interchangeable.

Threadrippers and Epycs also exist under the Zen 2 architectural umbrella, no?

[S w a t s o n]

Just now, thorhammerz said:

Threadrippers and Epycs also exist under the Zen 2 architectural umbrella, no?

They all use the same die, but it is right to try to not conflate Zen 2's packaging impacts vs the architectural impacts

[thorhammerz]

9 minutes ago, S w a t s o n said:

They all use the same die, but it is right to try to not conflate Zen 2's packaging impacts vs the architectural impacts

Isn't that what this whole circus is about? Everyone thinks they're talking about the same thing, when they're not (and accusations aside, it's not like anyone is wrong once the proper specific context is applied).

8 minutes ago, Drak3 said:

 

Nothing is known about TR 3000 yet and Epyc is unreleased.

While those products are unreleased (and let's say for the sake of argument, they never get released), while it's definitely easy (or perhaps "natural") to conflate Ryzen 3000 (more specifically, the R3/R5/R7/R9 SKUs on the AM4 socket) and Zen 2 (the architectural design of this generation of CPUs / SoCs) as the same thing, there is quite a fine line to be drawn between the 2 concepts (especially when the aforementioned concepts become their own separate focus).

 

 

[leadeater]

5 hours ago, S w a t s o n said:

-snip-

If every Zen2 CPU is unable to surpass 4.3Ghz all core (on ambient) then it is completely fair to use the term clock wall. Whether it be a single core clock wall of X or all core clock wall of Y in both cases you aren't going past it just as much as you can't run through a brick wall hence why people will say 'clock wall", you cannot go through it.

 

If you want to argue that you must always specify in which context sure, but no one actually cares all that much when it doesn't actually change the outcome.

 

The other problem is so few things are actually single thread, like really actually single thread or even just two Ryzen 3000 CPUs rarely get a chance to boost much because of PPT limits. Any core that wants to boost gets slammed down by the power limits very quickly so you are either not boosting or only boosted for a second or two. Functionally in real application usages the boost spec doesn't matter much at all because of this.

 

I can engineer a test use case to show single core boost however I cannot do the same to actual applications and games.

[mr moose]

34 minutes ago, leadeater said:

If every Zen2 CPU is unable to surpass 4.3Ghz all core (on ambient) then it is completely fair to use the term clock wall. Whether it be a single core clock wall of X or all core clock wall of Y in both cases you aren't going past it just as much as you can't run through a brick wall hence why people will say 'clock wall", you cannot go through it.

 

If you want to argue that you must always specify in which context sure, but no one actually cares all that much when it doesn't actually change the outcome.

 

The other problem is so few things are actually single thread, like really actually single thread or even just two Ryzen 3000 CPUs rarely get a chance to boost much because of PPT limits. Any core that wants to boost gets slammed down by the power limits very quickly so you are either not boosting or only boosted for a second or two. Functionally in real application usages the boost spec doesn't matter much at all because of this.

 

I can engineer a test use case to show single core boost however I cannot do the same to actual applications and games.

No matter how much we try to cool this thread, I believe it has hit a posting wall. 

[leadeater]

6 hours ago, S w a t s o n said:

There is nothing inherent in the architecture that requires it to clock slower.

Sure there is, there are many factors in an architecture that impacts the clocks it can operate irrespective of which fab or node. How each of these is effected by that architecture may be different but architecture plays a crucial role in how a CPU can clock. The old GF 14nm is capable of clocking much higher than 4Ghz, just not in a joint implementation of it and Zen/Zen+.

 

You could take Zen+ and increase the pipeline stages from 19 to 30-31 (like Netburst) and be able to clock it higher, but there is no free lunch here which is why modern pipeline stages have reduced back down from that 2006 ish era.

 

We simply cannot point to a fab/node and attribute that as the reason a CPU cannot clock higher, it may in fact currently be a minor reason as to why, or a major reason but we don't know as we are not the product engineers with that knowledge.

 

What has been the case for both AMD and Intel is that over successive iterations of architectures CPU clocks did not increase greatly. Intel was on 3.9Ghz across 32nm CMOS and 22nm FinFET as well as 14nm being 4.2Ghz. There were later revisions of architectures on some of the nodes that increased the clocks i.e. Devil's Canyon and what allowed those increases were architecture related and used the same node as Haswell. Two architectures, very closely related, on the same node clocking differently. It is these common trends that made me highly skeptical of 5Ghz claims, not that clocks would increase, but to this higher degree which is unprecedented in modern node shrinks (32nm and below). 

[leadeater]

6 minutes ago, mr moose said:

No matter how much we try to cool this thread, I believe it has hit a posting wall. 

[RejZoR]

I mean, it's not rocket science. AMD uses absolute boosting, Intel uses temporal boosting. AMD will boost as high as it can within its specs at all times. If you run something for 3 hours, it'll boost as high as it'll go through all this time at about same level. Where Intel, it boosts as high as it can for a short time (basically overdrive), even if that means hitting thermal limits and downclocking as a result. If you cool it enough for it to not hit that, it'll still stop boosting over time and drop the clocks anyway because that's how their boost works. Intel sort of has an edge at short tasks where it can complete them while overdrive doesn't even time out yet.

 

As for AMD, 3900X for example will hit 4.6GHz only for single threaded things and can run that till completion, but only if it's 1 thread the entire time. As soon as you start loading extra cores, the clock will start dropping.

 

1c=4.6GHz

2c=4.5GHz

3-4c=4.4GHz

+4c=4.3GHz

 

Assuming it's adequately cooled. Check GamersNexus for the exact load scaling of the clocks on 3900X, but iirc it was something like this. Load probably also depends, for example if something is loading all the cores, but not to their max capacity. I'm guessing in that case, all core clocks will be higher. But haven't seen that since all reviewers always use max possible load.

[cj09beira]

5 hours ago, Blademaster91 said:

No you're still making these claims that "not every chip has a clock wall" Yeah, a select few chips can hit higher, but look how much SilliconLottery wants for a 3800X that is guaranteed for 4.3Ghz. It isn't very likely to get a chip that isn't affected by what is effectively a clock wall.

And you just said it yourself, its hitting a wall regardless of single or multicore, 4.3Ghz is effectively the limit except for a few golden samples of the already high end chips that AMD does their own binning on.

The thing is if you go and look at siliconlottery's web site states that their 4.3Ghz all core overclock is done at 1.25 volts, which is a lot lower than what others needed to achieve their 4.3-4.4ghz overclock, i dont know why they choose such a low voltage but i already asked them about it, so with the max safe voltage being near 1.35v as amd said clocks would be higher.

1 hour ago, leadeater said:

If every Zen2 CPU is unable to surpass 4.3Ghz all core (on ambient) then it is completely fair to use the term clock wall. Whether it be a single core clock wall of X or all core clock wall of Y in both cases you aren't going past it just as much as you can't run through a brick wall hence why people will say 'clock wall", you cannot go through it.

 

If you want to argue that you must always specify in which context sure, but no one actually cares all that much when it doesn't actually change the outcome.

 

The other problem is so few things are actually single thread, like really actually single thread or even just two Ryzen 3000 CPUs rarely get a chance to boost much because of PPT limits. Any core that wants to boost gets slammed down by the power limits very quickly so you are either not boosting or only boosted for a second or two. Functionally in real application usages the boost spec doesn't matter much at all because of this.

 

I can engineer a test use case to show single core boost however I cannot do the same to actual applications and games.

no its not, you would not say that 9900k has a clock wall just because you reached max safe voltage, clock walls refers to when extra voltage does very little to clock speeds, and considering the fact that zen 2 will clock to 4.6ghz (for now with the current skus) on a single core that tells you it doesn't have a clock wall, now another thing to keep in mind is that people have figured out that the 3900x has a good die and a bad one, and people are finding that overclocking each die on its own gives considerable performance gains, as in going from max 4.3 to 4.3 on the worst die and 4.4-4.5 on the good one, this shows a bit of what is happening here, to save costs and improve yields amd even on the 3900x is not using 2 good clocking dies which also answer a question i had about the clocks per thread being used which seemed to have a pretty noticeable step in the middle while i expected as smooth as zen+ or better.

 

as i expected the chiplet design is having a major effect on overclocking headroom for the lower end chips, though i did not expect amd to go ahead and put one slow one even on the 3900x, they must be really needing those good ones for epyc, 

[leadeater]

7 minutes ago, cj09beira said:

no its not, you would not say that 9900k has a clock wall just because you reached max safe voltage, clock walls refers to when extra voltage does very little to clock speeds, and considering the fact that zen 2 will clock to 4.6ghz (for now with the current skus) on a single core that tells you it doesn't have a clock wall, now another thing to keep in mind is that people have figured out that the 3900x has a good die and a bad one, and people are finding that overclocking each die on its own gives considerable performance gains, as in going from max 4.3 to 4.3 on the worst die and 4.4-4.5 on the good one, this shows a bit of what is happening here, to save costs and improve yields amd even on the 3900x is not using 2 good clocking dies which also answer a question i had about the clocks per thread being used which seemed to have a pretty noticeable step in the middle while i expected as smooth as zen+ or better.

I wouldn't use clock wall at all but for the 9900K you can equally say it has a clock wall just the same. It makes no real difference, there is a point regradless of vcore where you cannot clock higher and must lower the tdie temperature to go further i.e. LN2. You can also do the same on Intel CPUs, multipliers aren't fixed across all cores and you can, people have, increased clocks on single better cores. These are more in the academic/fun realm than anything else as the performance gains are actually minimal, CB cores don't equate to observable performance increases but if your goal is to get the highest CB score you can then all the power to you.

 

Benchmarking is fun so there isn't a reason to no do it after all.

[yolosnail]

6 minutes ago, cj09beira said:

though i did not expect amd to go ahead and put one slow one even on the 3900x

It wouldn't make sense for AMD to put in two good chips if the higher clocks are only <4 core. It makes sense to use one good chip that can clock high, which can be used for lightly threaded tasks, and one chip that clocks lower  for the heavily threaded task as both chips will be limited to 4.3 anyway

[S w a t s o n]

1 hour ago, leadeater said:

Sure there is, there are many factors in an architecture that impacts the clocks it can operate irrespective of which fab or node. How each of these is effected by that architecture may be different but architecture plays a crucial role in how a CPU can clock. The old GF 14nm is capable of clocking much higher than 4Ghz, just not in a joint implementation of it and Zen/Zen+.

 

You could take Zen+ and increase the pipeline stages from 19 to 30-31 (like Netburst) and be able to clock it higher, but there is no free lunch here which is why modern pipeline stages have reduced back down from that 2006 ish era.

 

We simply cannot point to a fab/node and attribute that as the reason a CPU cannot clock higher, it may in fact currently be a minor reason as to why, or a major reason but we don't know as we are not the product engineers with that knowledge.

 

What has been the case for both AMD and Intel is that over successive iterations of architectures CPU clocks did not increase greatly. Intel was on 3.9Ghz across 32nm CMOS and 22nm FinFET as well as 14nm being 4.2Ghz. There were later revisions of architectures on some of the nodes that increased the clocks i.e. Devil's Canyon and what allowed those increases were architecture related and used the same node as Haswell. Two architectures, very closely related, on the same node clocking differently. It is these common trends that made me highly skeptical of 5Ghz claims, not that clocks would increase, but to this higher degree which is unprecedented in modern node shrinks (32nm and below). 

I understand how it works in general, I'm telling you that specifically in Zen's case there is no reason it needs to clock that much slower. I also disagree that devil's canyon had that much of an architectural increase in clock speed. It was literally haswell refresh, not that much changed, and we would expect higher clocks because they keep using the same shit so they optimize.

2 hours ago, leadeater said:

If every Zen2 CPU is unable to surpass 4.3Ghz all core (on ambient) then it is completely fair to use the term clock wall. Whether it be a single core clock wall of X or all core clock wall of Y in both cases you aren't going past it just as much as you can't run through a brick wall hence why people will say 'clock wall", you cannot go through it

I mean you're just using the term wrong and that's wrong. Zen 2 does have a distribution above 4.3GHz all core, as people can reach 4.4 and 4.5GHz, just like you can do higher than 5GHz all core on the 9900k.

It's only a clock wall if nearly every chip is stopped dead there because none of them can surpass it, not even golden samples. Clearly we see Ryzen 3000 can do 4.5GHz on golden samples.

Also the clock wall is not exactly the same as the voltage scaling curve/wall though they are related. Zen 1 has a true voltage scaling and clock wall. Zen 2 has a voltage scaling wall like any CPU for all-core but there's no clock wall.

[cj09beira]

20 minutes ago, yolosnail said:

It wouldn't make sense for AMD to put in two good chips if the higher clocks are only <4 core. It makes sense to use one good chip that can clock high, which can be used for lightly threaded tasks, and one chip that clocks lower  for the heavily threaded task as both chips will be limited to 4.3 anyway

at stock sure, but when i am paying 500 bucks for a cpu i expect good bins, giving me half a good bin is annoying, though i understand why they did it

[yolosnail]

Just now, cj09beira said:

at stock sure, but when i am paying 500 bucks for a cpu i expect good bins, giving me half a good bin is annoying, though i understand why they did it

If the 3900X was AMD's highest end CPU, then I would agree with you, but they'll be saving as many good chips as possible for the 3950X and of course for the single chip CPUs 

[leadeater]

31 minutes ago, S w a t s o n said:

It was literally haswell refresh, not that much changed, and we would expect higher clocks because they keep using the same shit so they optimize.

Yes which was exactly the point, same node, exactly the same node, with only an architecture tweak and gained 500Mhz single core boost. That's actually pretty good honestly. The problem with the 5GHz expectation was that equated to a 700Mhz increase which is right in the unrealistic area of expectation. Much of the anticipated gains people were expecting was from the shift from GF to TSMC and 7nm, evidence shows these types of moves and shrinks does not equate to large clocks gains. The majority of clock gains have come from architecture improvements, ones targeted to increase clocks.

 

Zen2 had to counteract both an expected clock reduction from 7nm due to internal resistance increase and a higher power target per core due to increased FPU bit width, two changes that inhibit increasing clocks. AMD and TSMC did an excellent job in being able to increase the clocks, very excellent job.

 

That doesn't change this issue that these points were raised before Zen2 launch and continuously brushed off, as well as the clock trend point. Why expect the unrealistic, why hope for something so unlikely? Why as it got closer you have some reviewers outright say 5Ghz is not happening prefer to believe 5Ghz rumors when that is the single piece of information that would back that against multiple others pointing towards it not being a thing.

 

Hindsight is a thing, but honestly hindsight was not required to know 5Ghz was so unlikely to happen it really wasn't worth talking like it was a possibility at that stage.

 

31 minutes ago, S w a t s o n said:

I mean you're just using the term wrong and that's wrong

I only use that term when others use to it address that fact it was used.

 

31 minutes ago, S w a t s o n said:

Also the clock wall is not exactly the same as the voltage scaling curve/wall though they are related. Zen 1 has a true voltage scaling and clock wall. Zen 2 has a voltage scaling wall like any CPU for all-core but there's no clock wall.

Zen1 and Zen+ didn't have a clock wall either, both can clock higher with LN2 just the same as any other CPU. Zen2 won't clock higher with increased vcore, it's not about unsafe or the temperature caused by the vcore increase it's about the chemical properties and how they act at lower temperatures. You can bring the CPU down to say 10C and no matter how much you pump the vcore up and leave it consistently at 10C while doing it the maximum attainable clock will not increase, lower temperature is required.

 

There is a point where increasing vcore will net you nothing and is entirely temperature dependent. If you've watched a number of LN2 overclocking videos you would have seen this in action whether you took much note of it or not.