When your RAM goes faster than your CPU - Micron DDR5-5100 tested

[williamcll]

Interestingly, AMD CPUs and chipsets have support for it

Translated from Chinese:

Quote

First to say sorry because of NDA I cannot say what models these are so some information are covered:

Current view Micron series of 2GB chips are in the best physical condition, single rank 16GB on the single-sided PCB is not having any pressure at all and tolerable to high frequency~
Perhaps on the AMD platform, this does not represent performance, but because it saves time, XD.

Okay, uploading the pictures:
First picture is that the memory has a factory setting of XMP 5000.


Let's supplement the DDR4-5100 during the previous experiment.



Then wait for the memory factory to mass-produce!
After all, there is no solution to how the memory factory takes a memory to form a stick!!

Source: https://www.chiphell.com/thread-2200976-1-1.html

Thoughts: The numbers look impressive but the Latency looks horrible, I also imagine the price to be ludicrous at least for a year.

[Doobeedoo]

Yeah nice, definitely would be great to see it with tighter timings indeed. Something around CL20 for example.

[MageTank]

1 hour ago, williamcll said:

Interestingly, AMD CPUs and chipsets have support for it

Translated from Chinese:

Source: https://www.chiphell.com/thread-2200976-1-1.html

Thoughts: The numbers look impressive but the Latency looks horrible, I also imagine the price to be ludicrous at least for a year.

How so? 5100 C18 translates to roughly 7ns absolute latency, which is far lower than XMP's, and lower than that of my own 4000 C15 configuration. In fact, it's so tight that I simply do not believe it. Aside from Micron's recent E-Die success, they have not been known for high speed, low latency IC's. To release something like this out of the woodworks with nothing preceding to any close degree, just doesn't seem possible.

 

To put this into context, the best Samsung IC's available on the market are 4800 C18 which translates to roughly 7.5ns. Considering B-Die's evolution and refinements over the years, it's far more believable that they achieved 7.5ns through incremental improvements rather than simply launch an IC at record latency and skipping over all other competitors.

 

If Micron really managed to pull this off, then hats off to them. I'll still wait for an actual physical sample before I believe it.

[porina]

I wonder if the minimum module size will also increase. On DDR4 I never saw 2GB modules, 4GB are uncommon now, and 8GB seems to be the starting point. As nice as this speed bump is, I don't want to give up either dual rank (only really found on 16+GB DDR4 modules now) or doing 2DPC, which is where the smaller module size helps out on cost.

 

9 minutes ago, MageTank said:

How so? 5100 C18 translates to roughly 7ns absolute latency

How much of it is down to CAS, as opposed to the "other" primary timings? Those are often same or only a couple more clock cycles on them, but the gap might be growing here.

[MageTank]

3 hours ago, porina said:

I wonder if the minimum module size will also increase. On DDR4 I never saw 2GB modules, 4GB are uncommon now, and 8GB seems to be the starting point. As nice as this speed bump is, I don't want to give up either dual rank (only really found on 16+GB DDR4 modules now) or doing 2DPC, which is where the smaller module size helps out on cost.

 

How much of it is down to CAS, as opposed to the "other" primary timings? Those are often same or only a couple more clock cycles on them, but the gap might be growing here.

In terms of overall latency, those other primary timings are often inconsequential. The important figure is Round Trip Latency (RTL), which is the sum of your primary, secondary and tertiary timings and their impact on overall latency. If you had the choice between tighter primaries (tRCD, tRP, tRAS) or tighter tertiary timings, I'd take the tighter tertiary timings. The improvement in bandwidth efficiency will have a positive impact on latency anyways.

 

This large of a gap isn't uncommon on DDR4 4600+ B-Die kits:

 

Or Hynix CJR in general, where you see 3600 C16-19-19 as the norm on budget modules. It's easier on the memory controller and doesn't impact overall performance all that much if any. You'll also see this on LN2 benches where people will run 4000+ CL12 flat, or CL12-16-16 depending on the board. As long as they can get high frequency and low CAS with the proper secondary/tertiary timings dialed in, they are good to go.

[RejZoR]

Well, it's always been like this, that initial versions of new DDR have timings so high that it often doesn't quite make sense to use them compared to super mature last gen DDR version at insane speeds and low timings. But as time progresses and DDR5 matures, it'll surpass everything DDR4 ever offered. Story will repeat once DDR6 is launched.

[porina]

13 minutes ago, MageTank said:

This large of a gap isn't uncommon on DDR4 4600+ B-Die kits:

I'm a filthy peasant in that my fastest kit is the HyperX 4000 (I think it is B-die), and even that I find gives better results on both Intel and AMD when run at its built in XMP 3600 profile. Presumably because some other timings are so much better at the lower speed. And for my uses, even at 3600 it is slower than dual rank 3200 kits.

 

Faster ram helps, but I'd still like to keep to either dual rank or 2DPC where performance really matters.

[DildorTheDecent]

Zoom.

[MageTank]

15 minutes ago, porina said:

I'm a filthy peasant in that my fastest kit is the HyperX 4000 (I think it is B-die), and even that I find gives better results on both Intel and AMD when run at its built in XMP 3600 profile. Presumably because some other timings are so much better at the lower speed. And for my uses, even at 3600 it is slower than dual rank 3200 kits.

 

Faster ram helps, but I'd still like to keep to either dual rank or 2DPC where performance really matters.

Oh, I 100% agree with you. I have a 4400 C19 kit that I run at 4000 C15-15-15-30-2 because it's easier on my IMC and runs better than the higher clock speed XMP. Any time you have to sacrifice on latency for bandwidth (from a consumer-grade software perspective), it isn't worth it. It's also not worth sacrificing on your tertiary timings to force a higher clock speed when you end up with less bandwidth due to poor bandwidth efficiency and even higher latency as a result.

 

As for single vs dual rank, this won't matter too much on DDR5. Traditional rank interleaving allows you to read from one rank while still writing to another, but DDR5 will bring simultaneous read/writes from within the same bank. They halved the bus sizes for the memory chips themselves, then doubled the number of buses. Multiple 7-bit ADDR/CMD buses on the same instance of memory. It's definitely going to be exciting when we get our hands on DDR5 in the consumer space, I honestly can't wait. 

 

The real question is, will rank interleaving on top of bank interleaving result in even more performance... 

 

EDIT: Clarified the confusing bus changes for DDR5.

[porina]

1 minute ago, MageTank said:

As for single vs dual rank, this won't matter too much on DDR5. Traditional rank interleaving allows you to read from one rank while still writing to another, but DDR5 will bring simultaneous read/writes from within the same bank. They halved the buses for the memory chips themselves, then doubled them. It's definitely going to be exciting when we get our hands on DDR5 in the consumer space, I honestly can't wait. 

I hadn't looked at the technology closely yet. My expectations were no more than "DDR4 but faster". If it does more than that, I wouldn't say no.

[MageTank]

6 minutes ago, porina said:

I hadn't looked at the technology closely yet. My expectations were no more than "DDR4 but faster". If it does more than that, I wouldn't say no.

I am trying to find Micron's actual whitesheets on the detailed changes, but you can find a short list here comparing DDR4 and DDR5: https://www.micron.com/products/dram/ddr5-sdram

 

EDIT: Nevermind. Right as I posted this, I found it: https://www.micron.com/-/media/client/global/documents/products/white-paper/ddr5_more_than_a_generational_update_wp.pdf. 

 

[The1Dickens]

Quote

"For example, DDR5 DIMMs feature two 40-bit (32 bits plus ECC) independent channels."

Is that normal on RAM, or does this mean all DDR5 will be ECC? Or will those bits be disabled on consumer-level kits?

[GoldenLag]

33 minutes ago, comander said:

RAM is generally measured/marketed in transfers per second

its usually marketed in mhz, but technically measured in Megatransfers. 

33 minutes ago, comander said:

The MHz states is a bit of a misnomer

but its sadly what the current marketing teams use, not to mention the metric that buyers look at. 

33 minutes ago, comander said:

MT/s is NOT the same thing as MHz

true, but you can technically twist Mhz to be correct aswell. 

 

providing it describes the rate of transfers, and not the rate at which it cycles. its dumb, but at this point we have lived with it for so many years there is no point arguing about it.

[MageTank]

2 hours ago, comander said:

MT/s is NOT the same thing as MHz

RAM is generally measured/marketed in transfers per second, not cycles. The MHz states is a bit of a misnomer. 

This is splitting hairs. While it's true they are not the same (DDR4 "3200mhz" is actually 1600mhz, 3200MT/s), we've come to recognize the term "effective clock speed". It's not inherently incorrect to say "DDR4 3200mhz" if on a double data rate DIMM, you're getting the effective bandwidth of a 3200mhz clock speed (1600 x 2).

 

We can argue literal vs colloquial terms all day, but at the end of the day it only matters that we all understand what the others mean when they are referring to something, and I am certain we all do when we see "DDR* XXXX".

 

13 hours ago, The1Dickens said:

Is that normal on RAM, or does this mean all DDR5 will be ECC? Or will those bits be disabled on consumer-level kits?

If it's anything like past releases, the check bits simply won't exist on non-ECC consumer modules. Sadly none of the DDR5 consumer whitesheets exist because they are launching with server/HPC markets in mind, and are starting off with ECC DIMM's. I am still confident that the bank interleaving feature will exist on consumer grade kits, just not as a function of ECC.

[MageTank]

13 minutes ago, comander said:

By that rationale a 3990x at 4Ghz is 4x64... 256GHz. 

Your analogy is a little off. Remember, the key wording is "effective clock speed". The effective clock speed of a CPU is derived from the core/bus ratio (CPU multiplier) multiplied by the actual core/bus clock. Using this analogy for RAM, the bus ratio would be 2 (double data rate) multiplied by the bus clock speed (1600mhz) to get an effective clock of 3200mhz, or 3200MT/s. If we are going to continue with your anaology of the 3990X, it would be core/bus ratio (40) multiplied by the core/bus clock of 100 (by default) to get 4ghz effective clock speed.

 

While individual cores can be linked to and communicate through a bus, they are not buses themselves. Again, we can argue the correct terms all day long, but you're going against the ocean on that one, especially since most marketing teams have already gone all-in on "effective clock speeds". Whatever is easiest to understand for the masses is typically what becomes the norm.

 

Besides, if you really wanted to muddy the waters with analogies to counter the effective clock speed argument, you could ask if multi-channel configurations impact effective clock speeds, lol.

[Bombastinator]

On 3/18/2020 at 11:22 AM, MageTank said:

How so? 5100 C18 translates to roughly 7ns absolute latency, which is far lower than XMP's, and lower than that of my own 4000 C15 configuration. In fact, it's so tight that I simply do not believe it. Aside from Micron's recent E-Die success, they have not been known for high speed, low latency IC's. To release something like this out of the woodworks with nothing preceding to any close degree, just doesn't seem possible.

 

To put this into context, the best Samsung IC's available on the market are 4800 C18 which translates to roughly 7.5ns. Considering B-Die's evolution and refinements over the years, it's far more believable that they achieved 7.5ns through incremental improvements rather than simply launch an IC at record latency and skipping over all other competitors.

 

If Micron really managed to pull this off, then hats off to them. I'll still wait for an actual physical sample before I believe it.

I’m a Bit confused here.  statement A was a request to tighten timings, but the statement B is the timings are already tighter than what he wished they’d be tightened to?

[MageTank]

9 minutes ago, Bombastinator said:

I’m a Bit confused here.  statement A was a request to tighten timings, but the statement B is the timings are already tighter than what he wished they’d be tightened to?

I am equally confused by the information provided in OP's post, because the screenshots are total contradictions of themselves, but I may have misunderstood things. What I saw in the screenshots were a supposed 5100mhz C18-26-26-46-1 configuration which is extremely tight given the actual memory clock speed (or megatransfers, to appease all parties). However OP stated:

On 3/18/2020 at 11:09 AM, williamcll said:

Thoughts: The numbers look impressive but the Latency looks horrible, I also imagine the price to be ludicrous at least for a year.

If the latency looks horrible at 7ns absolute, then I am at a loss because that's lower than any latency currently available on the market and destroys that of my own manual memory overclocks by a very fair margin. 

 

10 minutes ago, comander said:

TImings are relative. 

DDR1-400 CL1.5 (remember when HALF timings were a thing?) is comparable to DDR2-800 3-3-3 and DDR3-1600 6-6-6 and DDR4-3200 12-12-12 and DDR5-6400 24-24-24


Timings in and of themselves are meaningless without the context of the memory clock. 

This is correct. Latency (or primary timings in general) is worthless without the added context of clock speed and secondary/tertiary timings trained by the memory controller in conjunction with the motherboard. Even with a high clock speed/tight primary timings, you can still have less bandwidth and higher latency than a lower clocked, looser primary timing configuration if your RTL/IO-L offsets trained horribly due to poor secondary/tertiary values. This is why I often tell people to ignore XMP speeds and focus on picking good IC's and solid motherboards with the proper trace topology. At the end of the day, that's all that matters, aside from the IMC lottery, but there isn't any real advice to give there.

[SpaceGhostC2C]

On 3/18/2020 at 1:34 PM, porina said:

I wonder if the minimum module size will also increase. On DDR4 I never saw 2GB modules, 4GB are uncommon now, and 8GB seems to be the starting point.

I think these are (supposed to be) 2GB chips but 16GB modules, with 8x2GB chips in them.

 

[The1Dickens]

13 hours ago, MageTank said:

If it's anything like past releases, the check bits simply won't exist on non-ECC consumer modules. Sadly none of the DDR5 consumer whitesheets exist because they are launching with server/HPC markets in mind, and are starting off with ECC DIMM's. I am still confident that the bank interleaving feature will exist on consumer grade kits, just not as a function of ECC.

Okay, that makes sense.

 

6 hours ago, MageTank said:

it would be core/bus ratio (40) multiplied by the core/bus clock of 100 (by default) to get 4ghz effective clock speed.

I don't know exactly how to ask this, so pardon my ignorance: If the RAM is faster than the caches on the CPU, does that mean they can do with less caches (no L3, for example), or does that mean that the RAM will just never be "overwhelmed" (the bottleneck, I guess?)? I guess I was kind of under the impression that L3 (is there L4 now/yet?) was built out to store more "fast data" onto CPUs because they could burn through L1, L2, and possibly L3 faster than the RAM could supply it. This keeps the CPU chugging along with data to process while the slower parts of the system get the next 'batch of bits' to be processed. I guess ultimately the question I'm curious about is (and to not drive the thread off-topic into a ravine): how will/does RAM speeds affect CPU architecture, or is it the reverse that is true?

[Guest]

5000mhz on Ryzen is last years news. (6 months ago'ish)

 

Can purchase your very own set 16GB just a little under a G-Note.

Corsair LPX DDR4 5000mhz. 18-26-26-26-46 XMP 1.50v 

https://www.neweggbusiness.com/Product/Product.aspx?Item=9B-20-236-591&source=region&nm_mc=KNC-GoogleBiz-PC&cm_mmc=KNC-GoogleBiz-PC-_-pla-_-Memory+(Desktop+Memory)-_-9B-20-236-591&gclid=CjwKCAjwsMzzBRACEiwAx4lLG8ifb_3Lj6kz2Yp6s_UpwHeUfkWQ5V14PFrw8eLGmHLbfV2eCVIO1hoCmyMQAvD_BwE&gclsrc=aw.ds

 

When released this memory set was nearly 1900$. They've dropped 900$ in price in only 6 months due to very low demand.