Intel's 10nm Explained

[MandelFrac]

https://www.extremetech.com/computing/246902-intel-claims-three-year-advantage-10nm-process-wants-change-define-process-nodes

 

Recently we were told Intel was beginning bulk production for 10nm chips, meaning Cannonlake would arrive by year's end or Q1 2018 according to previous history and the usual 8-month lead time from bulk production announcement to products being on the shelves. However, now we have concrete detail from Intel's Mark Bohr on just why 10nm was such a painful node to master. It turns out Intel is introducing 2 patented techniques with this node which increased design complexity considerably in exchange for a 2.7x increase in transistor density.

Quote

Intel is claiming that its 10nm node will deliver a 2.7x improvement in transistor density compared with its 14nm products. That’s a significant jump over its 14nm products, and it’s not just the result of the improvements to various semiconductor manufacturing metrics. Intel has improved its 10nm scaling compared with 14nm through the use of two specific new technologies — single dummy gate, and contact-over-active-gate. Typically, logic cells use a pair of what are called “dummy gates” to isolate each cell from its neighbors. Intel has found a method of using just one dummy gate instead of using a pair of them, and has managed to recover significant space savings as a result.

 

Each gate has multiple contacts that connect to the metal layers within a CPU. Typically, these contacts are offset from the gate. At 10nm, Intel is moving the contact to directly under the gate, which frees up additional transistor space.

 

Further, Bohr contended that the traditional measurements used by ASML and others actually do not reflect the reality of how much tighter Intel has packed transistors. The metrics in use are accurate for Intel's competitors, for now, but he expects it will change for them soon too.

 

Quote

One simple metric is gate pitch (gate width plus spacing between transistor gates) multiplied by minimum metal pitch (interconnect line width plus spacing between lines), but this doesn’t incorporate logic cell design, which affects the true transistor density. Another metric, gate pitch multiplied by logic cell height, is a step in the right direction with regard to this deficiency. But neither of these takes into account some second order design rules…

 

At the other extreme, simply taking the total transistor count of a chip and dividing by its area is not meaningful because of the large number of design decisions that can affect it – factors such as cache sizes and performance targets can cause great variations in this value.

 

It’s time to resurrect a metric that was used in the past but fell out of favor several nodes ago. It is based on the transistor density of standard logic cells and includes weighting factors that account for typical designs. While there is a large variety of standard cells in any library, we can take one ubiquitous, very simple one – a 2-input NAND cell (4 transistors) – and one that is more complex but also very common: a scan flip flop (SFF). This leads to a previously accepted formula for transistor density:

(The weightings 0.6 and 0.4 reflect the ratio of very small and very large cells in typical designs.)

Every chip maker, when referring to a process node, should disclose its logic transistor density in units of MTr/mm2 (millions of transistors per square millimeter) as measured by this simple formula. Reverse engineering firms can readily verify the data.

In short, Intel has done so much work external to the traditional metrics, such as wiping out some components completely (the 2nd layer of dummy gates) and changing the way the copper contacts the gates, such as to cause the standard measure to not be representative. @Coaxialgamer actually fell into this trap on the previous thread. And, by a bit of napkin math comparing Intel's 10nm and TSMC's proposed 7nm nodes, Intel has achieved a ~30% lead in transistors/mm^2. As for how this eventually translates into performance, Intel says a 25% uplift is expected, and a 40% power drop is as well, but it's always workload-dependent as we know.

 

I actually was expecting Intel to bite the bullet and join IBM on the dark FDSOI-FinFET side, but with a material change already announced (with no specifics) for 7nm, it's not completely surprising that Intel wouldn't want to increase its wafer costs and even further complicate design rules now.

[GDRRiley]

interesting 

[Energycore]

Well just like everything else, I'll wait for reviews before stating what Intel's 10nm will be, but an interesting read nonetheless.

[Legolessed]

43 minutes ago, MandelFrac said:

https://www.extremetech.com/computing/246902-intel-claims-three-year-advantage-10nm-process-wants-change-define-process-nodes

 

Recently we were told Intel was beginning bulk production for 10nm chips, meaning Cannonlake would arrive by year's end or Q1 2018 according to previous history and the usual 8-month lead time from bulk production announcement to products being on the shelves. However, now we have concrete detail from Intel's Mark Bohr on just why 10nm was such a painful node to master. It turns out Intel is introducing 2 patented techniques with this node which increased design complexity considerably in exchange for a 2.7x reduction in transistor size.

 

Further, Bohr contended that the traditional measurements used by ASML and others actually do not reflect the reality of how much tighter Intel has packed transistors. The metrics in use are accurate for Intel's competitors, for now, but he expects it will change for them soon too.

 

In short, Intel has done so much work external to the traditional metrics, such as wiping out some components completely (the 2nd layer of dummy gates) and changing the way the copper contacts the gates, such as to cause the standard measure to not be representative. @Coaxialgamer actually fell into this trap on the previous thread. And, by a bit of napkin math comparing Intel's 10nm and TSMC's proposed 7nm nodes, Intel has achieved a ~30% lead in transistors/mm^2. As for how this eventually translates into performance, Intel says a 25% uplift is expected, and a 40% power drop is as well, but it's always workload-dependent as we know.

 

I actually was expecting Intel to bite the bullet and join IBM on the dark FDSOI-FinFET side, but with a material change already announced (with no specifics) for 7nm, it's not completely surprising that Intel wouldn't want to increase its wafer costs and even further complicate design rules now.

so naturally when it releases its only going to be implemented on their $500,000 cpu right?

[MandelFrac]

Just now, Legolessed said:

so naturally when it releases its only going to be implemented on their $500,000 cpu right?

Haha, no, laptop chips first.

[Legolessed]

2 minutes ago, MandelFrac said:

Haha, no, laptop chips first.

so if the cpu is $500k the laptops gonna be 10 million right? dang thats like the $40,000 apple watch

[MandelFrac]

1 minute ago, Legolessed said:

so if the cpu is $500k the laptops gonna be 10 million right? dang thats like the $40,000 apple watch

Also, don't quote the whole OP. Just delete everything in the quote block.

[Legolessed]

Just now, MandelFrac said:

Also, don't quote the whole OP. Just delete everything in the quote block.

ok sorry. i forgot, and its a little prank as well. for me i still got 30 minutes left of april fools!

[RadiatingLight]

2 hours ago, MandelFrac said:

2.7x reduction in transistor size.

No, a 2.7x increase in transistor density.

very different things.

[MandelFrac]

Just now, RadiatingLight said:

No, a 2.7x increase in transistor density.

very different things.

Good catch. Fixing.

[Sir Asvald]

reroast!

 

 

[MandelFrac]

Just now, Abdul201588 said:

reroast!

 

 

Nope, different source and different information.

[tlink]

will we see any meaningful performance increases?

[MandelFrac]

9 minutes ago, tlink said:

will we see any meaningful performance increases?

Intel is saying as much as 25% from the node, but we all know that's workload-dependent. Honestly I think the biggest change coming for performance is Intel doing the double-sized L2 the same way AMD did, because that's a very cheap way to get a 15-20% boost considering Ryzen's worse IPC but equal performance to Kaby Lake.

[Prysin]

5 hours ago, MandelFrac said:

Haha, no, laptop chips first.

according to intel it will be Xeons -> mobile -> desktop -> HEDT. In that order. Going forward with node shrinks.

[MandelFrac]

24 minutes ago, Prysin said:

according to intel it will be Xeons -> mobile -> desktop -> HEDT. In that order. Going forward with node shrinks.

I don't see Xeons being first given bulk production was just announced and Skylake E5 isn't even available yet.

[Prysin]

3 minutes ago, MandelFrac said:

I don't see Xeons being first given bulk production was just announced and Skylake E5 isn't even available yet.

intel said from now on, they will prioritize HPC/Enterprise first. Probably limited supply with certain partners. Official statement was made a month or so back. THis release plan only applies to future node shrinks. Skylake E5 is not a shrink

[NumLock21]

4 hours ago, Prysin said:

intel said from now on, they will prioritize HPC/Enterprise first. Probably limited supply with certain partners. Official statement was made a month or so back. THis release plan only applies to future node shrinks. Skylake E5 is not a shrink

Skylake xeon e5 is already out. Google has them and users can try them out too by registering for their cloud platform or something. Name for them, not sure if true are, xeon bronze, silver, gold, and platinum.

[MandelFrac]

12 hours ago, yian88 said:

does this mean 4c/8t i3's, 6c/12t i5 and 8c/16t i7 replacing the old generation i3/5/7 on price segment? or just 5% IPC improve,same core count and +-100 mhz?

if not 2.7x transistor is just bullshit CEO math, added fake slide numbers togheter 

Then when Cannonlake comes out we can get the transistor count and area, divide, and get our answer.

 

Also, no 4-core I3. Just 6-core mainstream I7. Dual-core processors are still really useful for office computers. As for performance increase, well, Intel's officially redesigned the L2 cache to be the same size as AMD's, so I see a good 15% improvement in performance per clock incoming, possibly more.

[3vitor]

This could be a great topic for TechQuickie. If someone tag the right people I would appreciate. I have no idea what their names are in here.

[Clanscorpia]

37 minutes ago, 3vitor said:

This could be a great topic for TechQuickie. If someone tag the right people I would appreciate. I have no idea what their names are in here.

They always read Tech news

[Nup]

These things will probably run hot, with so much density... will clocks be lower to compensate? I doubt the efficacy will manage to completely make up for it.