givingtnt

I can't wait for this to be instantaneously defeated.

I can't wait for this to be instantaneously defeated.

Motherboards are dumb expensive, you mentioned the price (which I mean, why are you even bothering if it's that ?) You'll lose a LOT on single core power and you won't get any advantages from the larger ("larger") thread count.

Compared to say, a 5800x it's useless.

Also, chill on the answer spamming. 

Summary
IBM has a product line know as IBM Z, some of you know what it is, and for those that don't its IBM mainframe offering, yep those old school room filling computers from the 70's and 80's, this is that, difference is that they are made with modern computer design philosophy, but these hulking beast can still run those programs made over 40 years ago. as for why they are still building modern day iterations of mainframes? well unlike your commodity x86 or ARM chip, these are the true battle tested tanks of the computer world that never stop, downtime on such systems is measured in milliseconds per year! (aka 99.9999% expected uptime) therefore are used on mission critical application such as banking transaction by the big banks of the world, also since they are optimized for such applications they are much faster at it, if said task was made to run on current day x86 or ARM servers, these beast would run circles around it.
 
With that introduction out of the way, IBM at hot chips unveiled their next gen Z mainframe processor, the IBM Telum the successor of the z15 architecture, which features a very radical departure from its predecessor design, the cache structure, as a bit of a primer, the previous gen z15 was made with 256MB of L3 cache for 12 cores (which is already an insane amount of cache) IBM paired four of these with a special processor that acted as system wide L4 cache with 960MB available, this paired is what IBM calls a unit, and then they put four of these units together to make a full mainframe system, the L4 cache chip is addressable to all the four units, and this what is sold to a customer, if you wanted one of those chips you had to buy the full system like this.
 
Now with the Telum they ditched both the special processor and the gigachad L3 cache, and they replaced all of it with a mega gigachad of 32MB of L2 cache per core, each chip has 8 cores paired with all that cache of a staggering total of 256MB of L2 cache, the same amount as the L3 available on the previous gen, now each L2 cache is private to each core like in a normal CPU, but now when a line of data gets evicted instead of going to RAM like it would on a conventional system, it gets tagged as L3 cache data and placed on available space in another core L2, effectively creating virtual L3 caching, yep the madlad engineers at IBM have created virtual on CPU caching system, (cue the mind blown meme here), but this doesn't stop here, there's still the L4 replacement, well it's the same as L3 but instead of a core in the same chips it goes to the cache of another chip in the system tagged as L4 cache data, and so now the madlads have created virtual on CPU L3 cache and virtual on system L4 cache!
 
to sum up an IBM Telum processor cache structure has 32MB of L2 private cache per core with 8 cores, then it has 256MB of virtual L3 cache on the processor and then it has 8GB! of virtual L4 cache! in a complete system, now a complete Telum system is made of a Telum chip, each chip is paired together with another chip on the same package for a duo of processor, then each package is paired with 3 other packages to form a four package unit, and finally a complete system is made out of four of these units, this gives a total of 32 chips on a system hence the total 8GB of L4 virtual cache. now the keen eye might have noticed this is less total cache that the previous gen chip, well IBM says that all of this changes (and not mentioned are the improvements to the core themselves as well as node process shrink from 14nm to 7nm) amounts to a 40% performance improvement over the previous gen z15, oh, the Telum system also amounts to 256 total cores BTW.
 
Also and this was mentioned in the comments in the article that a reader asked but a package has a TDP of ~400W so they are also toasty. honestly if you want a much better explanation go read the source or watch 🖥🖥🥔 video below.
 
Quotes
 
My thoughts
Just amazing, albeit all of this tech is made to run specific workloads for huge organizations, it can be an indicator for the future, AMD has V-cache coming soon to add 2 times more L3 cache to their CPU, and they made infinite cache for their GPU, Intel has sapphire rapids with HBM memory coming too and Nvidia perhaps might have something in their labs to tackle this and boost cache sizes to but we don't know, but it seems one part of the future for chips to get more performance is to boost cache sizes in novel ways, which makes sense RAM is somewhat getting stale, while DDR5 is coming with much higher bandwidth, it does not reduce latency, there's also another anadtech article, a preview of DDR5 and just looking at the specs numbers, latency on the higher frequencies tends to stay the same as current high frequency DDR4, ohh there's also samsung with PIM memory that attempts to offload some processing to RAM in order to increase bandwidth too.
 
All in all this decade seems to look setup to increase bandwidth and reduce latency in more novel ways that just make core go faster.
 
Sources
https://www.anandtech.com/show/16924/did-ibm-just-preview-the-future-of-caches
 

Lol this is so dumb.
Bezos can't win with nasa because their bid failed, so he takes it out on them / SpaceX anywhere he can.

I hope/doubt it would pass, this seems like it's clearly just trying to cause damage as retaliation.
And it's not like the internet Starlink provides through SpaceX is a government bid like it was with NASA.. there's nothing they can do about that lol.