What CPU has the most amount of L1 L2 L3 cache?

[columbusohio]

Hi there, I just watched the Linus Tech Tips CPU Caching video, which CPU (including server grade) has the most amount of L1 L2 L3 cache?

[DataEmo]

AMD 32 core CPUs will win the L3 cache race with 64MB and Intel 28 core Xeons will win the L2 category with 28MB

[mariushm]

What's the point of this question? The size isn't always everything, it also matters how you use it.

 

AMD EPYC server CPUs have 16 MB L2 cache and 64 MB cache (made out of 4 ryzen dies).

 

There's some other CPUs out there like IBM POWER8 with 96 MB L3 cache (2 dies with 48 MB each) or POWER 9 SU with 120 MB cache per chip

[Billy Pilgrim]

How much exactly does each level of cache effect performance? Just wondering.

[mariushm]

A lot. Here's for example how much disabling caches slows down older processors:

 

 

ps.  But just like with mechanical HDD caches, it only helps up to a point, when you go above some threshold adding more may give too little benefit compared to how much die space on the chip is wasted.

[Mira Yurizaki]

1 hour ago, Billy Pilgrim said:

How much exactly does each level of cache effect performance? Just wondering.

It depends on the design of the CPU. Adding another level of cache increases the latency of memory lookup in cache. There's a point where if you keep looking in cache, it would've taken as long, if not worse, than if you would've just looked it up in RAM in the first place.

 

Cache is also expensive, mostly in terms of die space it takes up. So having too much also eats into what that die space could've been used for. The following is a die shot of a Ryzen CCX. Notice how L3 cache takes up half the die space:

 

L1 and L2 cache are on the sides of the cores themselves, and it looks like it takes up roughly 20% of the die space per core.

 

Basically, you have a fine line between having just enough cache and having too little cache.

[Amazonsucks]

This one 

 

https://fuse.wikichip.org/news/941/isscc-2018-the-ibm-z14-microprocessor-and-system-control-design/

 

https://en.wikichip.org/wiki/ibm/microarchitectures/z14

 

Instruction L1 128KB per core(up to 10 per chip)

 

Data L1 128KB per core

 

Instruction L2 2MB per core

 

Data L2 4MB per core

 

Instruction L2 2MB per core

 

L3 128MB shared per chip

 

L4 672MB shared per drawer

 

The L4 cache containing SC chip is actually 9.7 billion transistors large on its own.

 

https://fuse.wikichip.org/news/941/isscc-2018-the-ibm-z14-microprocessor-and-system-control-design/2/

 

The max configuration of this system has 32TB(usable 40TB installed) Centaur DIMM RAIM, with each DIMM having its own buffer chip and 16MB cache. Each CPU has 5 DIMMs(the extra is for RAIM), for a total of 100 DIMMs in a max configuration system.

 

Yes that means this system supports 512GB DIMMs.

 

Max system would also have a total of 3GB of L3 cache, 2.6GB of L4 cache all capable of appearing as one seamless system to the OS.

 

[Mira Yurizaki]

If you're wondering what determines how much cache is needed and how many levels, it's hard to say what's definitive, but the main factor seems to be what is the penalty for accessing RAM.

 

A secondary factor is if they go with an inclusive policy, where the same data can be in multiple levels of cache, or exclusive policy, where data that's no longer needed in one level gets evicted to a higher level. There's pros and cons to both approaches, but an inclusive policy tends to require larger cache sizes