Ryzen 3000 series might have more than 8 cores

[leadeater]

43 minutes ago, Stefan Payne said:

the decision of not going to 256bit AVX decreased power consumption and is one of the reasons that AMD is as efficient as they are now. If they would increase it to 256bit AVX, it would increase power consumption and the Intel fans would come out with "get Intel, more Power Efficient"

And its not really much better on Desktop CPUs either...

It would only increase it for AVX2 workloads not AVX1 (or non AVX for that matter) and the actual operation is still more power efficient for the performance gain, it's just that it will use more power for the much larger performance gain.

 

That's why AVX-512 is such a big deal in the enterprise/HPC space even though it uses so much power, the performance gain far out strips the power increase and you can gate it anyway with AVX power/clock tables.

 

43 minutes ago, Stefan Payne said:

And why not go full GPGPU with that instead?! 

Even Wikipedia mentions GPGPU under "Vector Processor"...

https://en.wikipedia.org/wiki/Vector_processor#GPGPU

As to why not GPGPU, latency. As mentioned in your link moving data is power expensive and you're talking about having to move data out of system CPU cache, through system memory, to GPU memory, to GPU cache to then actually be able to some computational workload on it, then the entire process in reverse to get that back to the CPU. As you can probably tell the entire process would have an extremely high latency so overall effective performance on small or irregular workloads would be very low compared to doing it on the CPU even with the lower raw performance capability.

 

GPGPU is currently only good for larger or sustained workloads with little communication back to the CPU and no data dependencies on operations i.e. Mining.

 

That's why there is a such a big push in the industry for memory semantic protocols, the current big players being Gen-Z/CCIX/CAPI. When all devices in a system can communicate using a common protocol across a fabric you can do direct data loads from CPU cache to GPU cache without any translation layers or steps which are very expensive processes, not having to do them is the best option.

 

Whenever you have to move data you need to do the benefit versus cost analysis and the cost currently is always extremely high.

 

43 minutes ago, Stefan Payne said:

Especially since you have to widen all data transfer paths inside the CPU for 256bit AVX wich you only need for AVX2. Doesn't seem to make much sense, does it?

Zen can do AVX2 but it requires two memory write operations so no actual power saving on that side, not really anyway. More just a cost and die area saving decision on that one. AMD could increase the write port to 256bit and leave the FMA units at 128bit and still get a performance gain with no power increase on AVX2 computation, wouldn't be a large performance gain though.

[Mira Yurizaki]

29 minutes ago, Stefan Payne said:

And why not go full GPGPU with that instead?!

Because AVX is an extension of the x86 architecture. That means:

• It precludes the requirement of having a GPU in the first place which for some use cases is preferable.
• Being able to perform SIMD instructions within the same processor can be faster than having to offload it on the GPU. If you have small enough data sets, the GPU isn't going to be any faster than the CPU.
• It may benefit software based algorithms like x264.
• Because it's an extension to a common architecture, you may not have to have different versions depending on the manufacturer of the CPU. Unlike GPGPUs where you may have to have different versions, if you decide to go the route of supporting multiple manufacturers.

[wasab]

Gigarhertz war is over. Now it is about who has more cores.

[wasab]

On 7/19/2018 at 5:44 PM, orbitalbuzzsaw said:

AMD > $300 12-cores

Intel > AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

AMD > $50 quad cores 

Intel > AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

AMD > 7nm Vega

nVidia > AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

Intel > Cannon Lake?

AMD > haha 32 core threadripper

Nvidia is killing amd with their 1080ti

[Jito463]

5 hours ago, C2HWarrior said:

I wouldn't really include avx here because it's not a realistic workload for 99% of consumers. That's why amd didn't bother to focus on it. Perhaps they will use some of the extra space for better avx performance in zen2

I was mainly using it as an example of how different workloads can lead to different IPC results.  Ergo the conclusion that IPC is not a static number, but rather will vary based on what you're using the CPU for.  Overall though, I would argue that Ryzen is pretty close in IPC to Intel in most common workloads, it's really only the clock speed wall that's holding it back.

[NumLock21]

23 hours ago, leadeater said:

Depends on what you actually need, anyone wanting 10GbE and more than an M.2 or 2 would still go with TR even at the same core count as what Ryzen can do. Comes down to if you just have CPU performance requirements or higher end platform requirements, which is the bigger mistake Intel has done with their HEDT lineup.

 

Why would anyone want to step up to HEDT on Intel when half the product stack is artificially capped at a reduced lane count so motherboard AIC and M.2 utilization is a pain to figure out and you don't really have any more than the desktop line with all the cost of HEDT. Intel HEDT is purely a wallet competition at this point, all practically has been thrown out the window.

I agree that Intel Kaby Lake X with half of its features disabled was a stupid decision made by Intel. AMD on the other hand, yes both Ryzen and Threadripper both have 8 cores as an option, where Ryzen so far tops out at 8 cores, and Threadripper tops out at 16 cores. When Ryzen also gets 16 cores, then what is the point of Threadripper? Not may users is going to buy a 32 core cpu. To the average consumer, cpu core count sells. Ryzen with the amount of cores they need and being cheaper, they will buy that instead of Threadripper. These PCIe lanes, M.2, 10GbE, etc, there are technical stuffs, they're not going to care about it that much. I do hope whatever AMD is doing, isn't going to hurt on their HEDT platform.

20 hours ago, cj09beira said:

for some people yes but am4 still only gets 2 channel ram so i bet that in many cases the 12 cores on TR will be faster (same gen of course), plus TR is a beast of a platform with many features pulling people in

What features are we talking about where Threadripper has and Ryzen does not. Only us techies will care about this dual channel, quad channel, Threadripper having more PCIe lanes than Ryzen, etc. The average consumer won't care about any of that. Asrock X470 Taichi Ultimate features Aquantia 10GB Lan from Newegg cost $246. A few days ago it was as low as $206. Asrock Fatal1ty X399 Professional, also featuring Aquantia 10GB Lan at Newegg is going for $390, with its lowest price a few days ago at $354. At both their current price and their lowest price, the difference between them is $144 to $148 dollars. This much saved by going with Ryzen, means the money save can be used towards higher capacity storage, a faster video card, or a better monitor. Why spend more on Threadripper when Ryzen can offer it for a lot less. Marketing CPU core count, is the same as slapping the word gaming, it sells. By having Ryzen also increasing in core count, makes Threadripper a dying platform and I hope, it does not end like this.

[leadeater]

5 minutes ago, NumLock21 said:

I agree that Intel Kaby Lake X with half of its features disabled was a stupid decision made by Intel

I was actually referring to the Skylake-X SKUs with reduced PCIe lanes, what's this Kaby Lake-X stuff you're talking about? Never heard of it, I don't think it exists .

[leadeater]

13 minutes ago, NumLock21 said:

What features are we talking about where Threadripper has and Ryzen does not. Only us techies will care about this dual channel, quad channel, Threadripper having more PCIe lanes than Ryzen, etc. The average consumer won't care about any of that.

The average consumer won't be looking at X399 or X299 either though so the people that actually are do care and will have more requirements than just what the CPU can do alone. There will of course still be status symbol buyers but we don't actually have anything specific to cater for to those buyers other than big price tags.

 

Simple thing is on Ryzen you can't have two PCIe NVMe SSDs at full bandwidth as well as 10GbE, also a second GPU along with the former stuff as well. Right now my X79 system as two GPUs, Dual 10GbE NIC and a LSI RAID card which is an impossible config in Ryzen and Intel consumer.

[Taf the Ghost]

5 hours ago, leadeater said:

Plus Zen is not weak in AVX1, it's actually really good at that. It's just not good at AVX2. Issue is Intel doesn't have this behavior so there is no reason to not use AVX2 when it may not be required, on Zen it could be better to not use it in certain cases but you'd have to optimize in that way.

More technically, Zen just runs at half speed when running AVX2. AVX512 can wait 2 generations, but AVX2 units should be fully doable with the shrink, especially as AVX2 isn't much area on the 14nm dies of Intel. (AVX512 is a lot of space, which is why it isn't on consumer Intel parts.)

[Taf the Ghost]

5 hours ago, leadeater said:

Plus Zen is not weak in AVX1, it's actually really good at that. It's just not good at AVX2. Issue is Intel doesn't have this behavior so there is no reason to not use AVX2 when it may not be required, on Zen it could be better to not use it in certain cases but you'd have to optimize in that way.

Random thought, but I wonder if AMD will stick any more co-processors on Zen2. They have that AES accelerator, for Epyc & Ryzen Pro, on die. I'm curious if we're going to see more ASIC-type approaches get added. Not sure what is some oddly regular instruction type that could use it, but maybe something video related. though I imagine it'd be something to accelerate Database work.

[leadeater]

42 minutes ago, Taf the Ghost said:

Random thought, but I wonder if AMD will stick any more co-processors on Zen2. They have that AES accelerator, for Epyc & Ryzen Pro, on die. I'm curious if we're going to see more ASIC-type approaches get added. Not sure what is some oddly regular instruction type that could use it, but maybe something video related. though I imagine it'd be something to accelerate Database work.

Right now I'd say AMD have to stay rather workload agnostic and have good enough options in the server space to compete with Xeon Bronze through to Gold 5xxx, anything higher than that they don't have the market presence and confidence.

 

Getting notoriety back in the consumer space will be likely the most effective path back in to servers.

 

The only thing they could target specifically that would make it in to market would be stuff around networking and storage appliances which they are already doing in the EPYC embedded lineup, easier to get partnerships with equipment makers who can product test stuff at low risk and bring it to market than try and convince systems engineers that EPYC won't be a mistake to purchase.

 

51 minutes ago, Taf the Ghost said:

More technically, Zen just runs at half speed when running AVX2

Well that is the same thing as being not good at it, half as good isn't fully good . That's why widening the FMAs, if easily done, would be so effective and not a big architecture change from what I can tell. Plus if they did that by nature if they want they could have a single 512bit FMA (256 + 256) to do AVX-512 to compete with the Xeon Gold 5xxx and lower which only have one 512bit FMA.

 

I imagine there are many flow on effects from making the FMAs wider which is why it wasn't done in Zen or Zen+, things like larger caches which eat die space. All cost effective solvable issues at 7nm.

[Stefan Payne]

2 hours ago, leadeater said:

Simple thing is on Ryzen you can't have two PCIe NVMe SSDs at full bandwidth as well as 10GbE, also a second GPU along with the former stuff as well. Right now my X79 system as two GPUs, Dual 10GbE NIC and a LSI RAID card which is an impossible config in Ryzen and Intel consumer.

In theory that is possible but you have to sacrifice the Chipset.

In practice it is not because AM4 only implements 20 (some say 24 but that might either include Chipset or USB 3.1) of the 32 lanes the Ryzen CPU has.

 

But you are missing the 8 2.0 Lanes in the Chipset ;-)

 

Still what we have:
CPU with 32 lanes, where some ports of the PHY are either shared with S-ATA or USB

Socket that allows 24 lanes (might either include Chipset and/or CPU USB Ports)

Chipset with integrated PCIe switch that has an additional 8 Lanes...

Here is what I've found so far, sadly there isn't much Information about AM4. TR4 is better documented...

https://www.tweaktown.com/guides/8342/amd-x399-tr4-threadripper-motherboard-buyers-guide/index.html

[Taf the Ghost]

9 minutes ago, leadeater said:

Right now I'd say AMD have to stay rather workload agnostic and have good enough options in the server space to compete with Xeon Bronze through to Gold 5xxx, anything higher than that they don't have the market presence and confidence.

 

Getting notoriety back in the consumer space will be likely the most effective path back in to servers.

 

The only thing they could target specifically that would make it in to market would be stuff around networking and storage appliances which they are already doing in the EPYC embedded lineup, easier to get partnerships with equipment makers who can product test stuff at low risk and bring it to market than try and convince systems engineers that EPYC won't be a mistake to purchase.

 

Well that is the same thing as being not good at it, half as good isn't fully good . That's why widening the FMAs, if easily done, would be so effective and not a big architecture change from what I can tell. Plus if they did that by nature if they want they could have a single 512bit FMA (256 + 256) to do AVX-512 to compete with the Xeon Gold 5xxx and lower which only have one 512bit FMA.

 

I imagine there are many flow on effects from making the FMAs wider which is why it wasn't done in Zen or Zen+, things like larger caches which eat die space. All cost effective solvable issues at 7nm.

With a 1+1 combo unit for AVX512, it's likely Epyc would toast everything but Xeon Platinum in the AVX512 space due to the Octa-channel memory. AVX512 is actually too much memory bandwidth at the current specs to really be leveraged well. Phoronix's testing on that was quite insightful. AVX512 probably doesn't take off until DDR5 hits the Server space, where you can actually start to see the benefit of it. (That an Intel actually having a fully activate ISA.)

[Stefan Payne]

6 minutes ago, leadeater said:

That's why widening the FMAs, if easily done, would be so effective and not a big architecture change from what I can tell.

Naa, you need a complete redesign of the FPU, Scheduler and all the caches for that.

You rather double the FPU units than widen the paths for AVX2...

With what we have right now the "Hot Clock" thingy might also not be possible no more...

 

With that said and the changes that are speculated for NAVI, its possible that they might put a graphics core inside the next iteration of Ryzen and let the integrated GPU do that instead.

Or at least that might be the long term goal, to waste resources on increasing AVX might be a bit contra productive in the long term.

 

 

PS: It is speculated that AMD wanted to do a new, ground breaking FPU for Bulldozer but scrapped that...

Can't find the speculation about that right now, but it was caled TPU or "Technical Float Point Unit" or something like that.

[leadeater]

17 minutes ago, Stefan Payne said:

In theory that is possible but you have to sacrifice the Chipset.

In practice it is not because AM4 only implements 20 (some say 24 but that might either include Chipset or USB 3.1) of the 32 lanes the Ryzen CPU has.

 

But you are missing the 8 2.0 Lanes in the Chipset ;-)

 

Still what we have:
CPU with 32 lanes, where some ports of the PHY are either shared with S-ATA or USB

Socket that allows 24 lanes (might either include Chipset and/or CPU USB Ports)

Chipset with integrated PCIe switch that has an additional 8 Lanes...

Here is what I've found so far, sadly there isn't much Information about AM4. TR4 is better documented...

https://www.tweaktown.com/guides/8342/amd-x399-tr4-threadripper-motherboard-buyers-guide/index.html

This issue isn't specifically the number of lanes but how they get divided and allocated to slots, if any lane could be assigned anywhere then it would be a lot simpler but that's not how it works sadly.

 

On a typical X470 board you only have 3 PCIe slots physically larger than x1 but I have 4 devices that require x4 or larger and the two x4 devices will fully use those lanes so I can't end cut and live with x1.

 

With the fixed 16 to PCIe slot 1 and 2 (x16 or dual x8) you're pretty well screwed from that point on, though for me with dual GPU fine but then what about the RAID card and Dual port 10GbE? Both of those are a really bad idea to put on the chipset lanes both for system compatibility reasons and bandwidth between the chipset and CPU. If I had to I'd put the RAID card on the chipset as long as I wasn't booting from it otherwise direct to CPU only.

[leadeater]

2 minutes ago, Stefan Payne said:

Naa, you need a complete redesign of the FPU, Scheduler and all the caches for that.

You rather double the FPU units than widen the paths for AVX2...

Doubling the unit count is harder and less transistor and die space efficient while also having all the other requirements like larger caches. Making things wider is actually easy so long as you are willing to accept the die size increase and cost.

[leadeater]

27 minutes ago, Stefan Payne said:

With that said and the changes that are speculated for NAVI, its possible that they might put a graphics core inside the next iteration of Ryzen and let the integrated GPU do that instead.

Or at least that might be the long term goal, to waste resources on increasing AVX might be a bit contra productive in the long term.

Common workloads for AVX are genomics where they need 1TB+ ram, if you go back and watch the LTT video where Linus went to that Canadian university watch out for the part that covers the quad socket systems with no GPUs and the explanation as to why. Those servers are for AVX workloads and huge datasets that need all of it in ram all the time otherwise performance takes an extreme dive.

 

AVX isn't a waste, it's not even that much die area and the performance gain is immense. Not everyone might need full performance AVX2 or AVX-512 at all but if it only costs, random number here, $8 extra part cost to have in the CPU then it's not that bad. If you have it then you have potential customers, if you don't then you have less potential customers i.e. the ones that would use AVX2.

 

GPUs are fundamentally bad at a lot of thing which is why AVX exists as well as FPGA PCIe cards, they can do the work GPUs can't and never can.

[Taf the Ghost]

1 minute ago, leadeater said:

Doubling the unit count is harder and less transistor and die space efficient while also having all the other requirements like larger caches. Making things wider is actually easy so long as you are willing to accept the die size increase and cost.

Given the area shrink that comes with 7nm, and the already relatively small size of Zen cores, I've felt it's a pretty safe assumption that AMD would expand the FP capability. That plus better Cache management (apparently it's quite bad, relative to Intel) seems like the much easier areas that would gain them quite a lot of benefit from where a lot of the instructions are going.

 

Though the real part comes down to matching Intel for clocks, and the larger L3 that keeps being rumored probably points to the Core to Core efficiency increases being on the table.

[cj09beira]

15 hours ago, valdyrgramr said:

Well, you can get a 1950x for around 700-750 now, wasn't MSRP like 1000?  I'm getting a 1950x myself for Maya and other workstation tasks for now, and when TR2 drops down in price I'm going TR2 since my ASRock Taichi will support it via a bios update.  Not sure if they confirmed the price yet, but one of the TR2s "might" be released on August 13th from what I was told, but not sure if that is actually confirmed yet.

dont overclock the tr2 cpu or your board will die, 

[cj09beira]

1 minute ago, valdyrgramr said:

Good to know, but any reason why?  I haven't been following TR2 much.

because power per core at high clocks increased, add to that double the number of cores and it becomes really hard to supply that amount of amps (intel goes around this by having the vrms supplying the cpu at a higher voltage thus reducing the amount of current needed)

[Stefan Payne]

3 hours ago, leadeater said:

Common workloads for AVX are genomics where they need 1TB+ ram, if you go back and watch the LTT video where Linus went to that Canadian university watch out for the part that covers the quad socket systems with no GPUs and the explanation as to why. Those servers are for AVX workloads and huge datasets that need all of it in ram all the time otherwise performance takes an extreme dive.

That's where HBCC and HSA comes into play
Theoretical its possible to but then again we are talking about special situations.

The bigger Problem is that there is no fast interface for the GPU right now. That might Change with VEGA20 that will get the IF Thingy.

But that's still more of a specialized enviroment...

And due to "circumstances"; its highly unlikely that AMD will get a foot in there even if they have a better and cheaper product...

 

3 hours ago, leadeater said:

AVX isn't a waste, it's not even that much die area and the performance gain is immense. Not everyone might need full performance AVX2 or AVX-512 at all but if it only costs, random number here, $8 extra part cost to have in the CPU then it's not that bad. If you have it then you have potential customers, if you don't then you have less potential customers i.e. the ones that would use AVX2.

It is bad because its useless for most situations and only useful in some certain instances...

And AVX already runs pretty good.

3 hours ago, leadeater said:

GPUs are fundamentally bad at a lot of thing which is why AVX exists as well as FPGA PCIe cards, they can do the work GPUs can't and never can.

And with NAVI you hear stuff like big and little cores, that looks like it goes further in the GP-GPU direction and the implementation of IF in VEGA20.

 

[leadeater]

12 minutes ago, Stefan Payne said:

That's where HBCC and HSA comes into play
Theoretical its possible to but then again we are talking about special situations.

The bigger Problem is that there is no fast interface for the GPU right now. That might Change with VEGA20 that will get the IF Thingy.

But that's still more of a specialized enviroment...

And due to "circumstances"; its highly unlikely that AMD will get a foot in there even if they have a better and cheaper product...

That would solve some issues and allow more things to run on GPUs, the actual things that will solve that though is Gen-z, CCIX and CAPI but you need all 3 basically. HBCC and HSA are just bits of Gen-Z AMD took while helping develop those technologies and do early but limited implementations of them.

 

GPUs still can't run workloads that require higher bit accuracy though, they cap out at FP64 but even that's gone to the way side in recent times due to how much performance you actually get out of AVX and the larger memory requirements.

 

There's a HPE server prototype coming end of this year with AMD EPYC with Gen-Z support from what I've heard. 2019 should be the year of Gen-Z, in market product announcement wise not just tech talk about something being developed. Interesting times ahead. I'm also betting the 7nm Vega will have Gen-Z support and is a big reason it's not coming to, probably, gaming cards is because they are using the gained die area for Gen-Z controller not just lower power and better clocks. Though could all just be pipe dream and not be real at all, I'm just going to have wait impatiently.

 

12 minutes ago, Stefan Payne said:

It is bad because its useless for most situations and only useful in some certain instances...

And AVX already runs pretty good.

Plenty of things do use AVX2, pretty much anything involving video encoding and decoding. Handbrake being a good example. It's really not that big of a problem increasing the bit width of the FP units, it's extremely cheap transistor and die area wise so there isn't much reason not to and larger L1, L2 and L3 cache to support it help for everything anyway.

[cj09beira]

3 minutes ago, leadeater said:

There's a HPE server prototype coming end of this year with AMD EPYC with Gen-Z support from what I've heard. 2019 should be the year of Gen-Z, in market product announcement wise not just tech talk about something being developed. Interesting times ahead. I'm also betting the 7nm Vega will have Gen-Z support and is a big reason it's not coming to, probably, to gaming cards is because they are using the gained die area for Gen-Z controller not just lower power and better clocks. Though could all just be pipe dream and not be real at all, I'm just going to have wait impatiently.

 

thats good to know but would gen-z need that much die space ? 

[leadeater]

4 minutes ago, cj09beira said:

thats good to know but would gen-z need that much die space ? 

I have no idea, so little is known about it other than the protocol standards documentation and information.

[Stefan Payne]

20 minutes ago, cj09beira said:

thats good to know but would gen-z need that much die space ? 

The PHYs would take the biggest space. You can't downsize those much these days...

And the interface is already implemented in AMD Ryzen, you could take a Die Shot and compare it to a Polaris Die