AMD to publicily reveal new HW at Computex.

[leadeater]

5 minutes ago, pas008 said:

Where are you?

Seriously what conversation are you in

Well the conversation is about MCM GPUs and you're talking about things that are not related to MCM. SLI, Hydra, PCIe or anything external to the actual GPU die itself is like talking about driving a car but we need to fly a plane, totally different things.

 

If I need to hammer a nail in I don't use the end of my shoe, it might be a really nice shoe but it's totally useless at hammering nails in .

[cj09beira]

5 minutes ago, leadeater said:

Interestingly MCM and the rise of Raytracing might lead to the end of post processing which would eliminate a lot of issues MCM would have if you split up the rendering of frames in to zones independently. The problem of not rending a frame in full and instead stitching is making sure things like shadow maps, blur and bloom etc actually look the same across the frame and line up physically. Gaming experience wouldn't be great if the shadow of a tree was a different shade half way and was shifted to the right by 2 pixels.

the problem there would come from math errors (as in variance) coming from either the code or the gpu itself, i guess then that a titan v wouldn't be able to do it ,

the problem is that i don't know how precise those things are so i don't know if that would be hard or easy to achieve 

[leadeater]

5 minutes ago, cj09beira said:

the problem there would come from math errors (as in variance) coming from either the code or the gpu itself, i guess then that a titan v wouldn't be able to do it ,

the problem is that i don't know how precise those things are so i don't know if that would be hard or easy to achieve 

Post processing effects look at things around it so frame stitching means there is missing information and that effects that directly, it's not so much an error it's just not knowing what isn't there. If I gave you a picture of half a house then told you to draw the shadow of that house, then gave someone the other half of the image and told them to draw the shadow of their half then took both resulting pictures and tried to overlay them to make the full house the house would line up but the shadow might not Edit: and areas of the shadow might not be dark enough or light enough without knowing what was on the other half of the image.

[cj09beira]

1 minute ago, leadeater said:

Post processing effects look at things around it so frame stitching means there is missing information and that effects that directly, it's not so much an error it's just not knowing what isn't there. If I gave you a picture of half a house then told you to draw the shadow of that house, then gave someone the other half of the image and told them to draw the shadow of their half then took both resulting pictures and tried to overlay them to make the full house the house would line up but the shadow might not.

then its not much of a problem, you render slightly more than the quarter you need so that you then can have the needed info, it would lower performance a bit though  

[leadeater]

1 minute ago, cj09beira said:

then its not much of a problem, you render slightly more than the quarter you need so that you then can have the needed info, it would lower performance a bit though  

Wonder how hard that would be, it's the reason why SLI and Crossfire do AFR and not Split Frame Render though.

[cj09beira]

5 minutes ago, leadeater said:

Wonder how hard that would be, it's the reason why SLI and Crossfire do AFR and not Split Frame Render though.

sometimes having someone from the design teams would be cool, but i would guess they can't say much either  

[leadeater]

4 minutes ago, cj09beira said:

sometimes having someone from the design teams would be cool, but i would guess they can't say much either  

Wouldn't being a fly on the wall be amazing, I'd consider quitting my job just to sit around listening and watching the Intel and AMD teams design CPUs and GPUs lol.

[cj09beira]

Just now, leadeater said:

Wouldn't being a fly on the wall be amazing, I'd consider quitting my job just to sit around listening and watching the Intel and AMD teams design CPUs and GPUs lol.

if you find a way to do it, give me a call  

[asus killer]

4 hours ago, leadeater said:

Nvidia furnace Fermi? 480 ran as hot as the dual GPU 4870X2 lol.

yep, i just talking about recent times, but it's true

[Taf the Ghost]

55 minutes ago, cj09beira said:

sometimes having someone from the design teams would be cool, but i would guess they can't say much either  

 

1 hour ago, leadeater said:

Wonder how hard that would be, it's the reason why SLI and Crossfire do AFR and not Split Frame Render though.

Bring back true SLI! Scanline Interleave. (Seriously, it worked really well, even if you can't do that approach now.)

 

On the MCM with GPUs, people gave AdoredTV flack about the 5 chip Epyc theory, but there's something people really haven't noticed with Adored. He's got sources with information from AMD's R&D division. We know that because he gets to ideas a bit ahead of others. For a CPU, the stuff that could be, in theory, moved off die would be the SoC stuff, which really wouldn't save that much space.

 

But a 4-way MCM with a 5th Controller die makes a lot more sense for a GPU. You could use a 5th die as the entry & exit point of the rendered frame. You basically turn each full GPU die into a CU-like system. It would take a lot of planning & work, but that's also why I think Adored's information came from the deep R&D department. That's something they *should* be working on. If we can sit here and "game out" the advantages AMD could reap by going the full MCM route, one would hope AMD has been putting in the work.

 

I do think, at best, we'd only ever see 2-die MCM for consumer. Probably with the dies extremely close together, on a new interposer-type technology. (There's a few already coming into use & in the pipeline.) They'd probably do some interesting things to connect the dies, but the IF would probably be the Control Layer rather than the interconnect layer there. Or they find a way to put 10 IF links on a die, haha.

[leadeater]

3 minutes ago, Taf the Ghost said:

AdoredTV

Annnnnnnd.... ignored .

j/k

 

If there is going to be a 5th die then I do actually have a fair idea what it could be for, relates to my previous HPE prototype comment. I never asked if I could talk about it so I'll take the shut up and wait for Computex approach and if it doesn't show up there then I'll know it's confidential. It's not super secret stuff or anything but still a good idea not to annoy our HPE account manager, it's some very important tech for AMD.

[cj09beira]

13 minutes ago, leadeater said:

Annnnnnnd.... ignored .

j/k

 

If there is going to be a 5th die then I do actually have a fair idea what it could be for, relates to my previous HPE prototype comment. I never asked if I could talk about it so I'll take the shut up and wait for Computex approach and if it doesn't show up there then I'll know it's confidential. It's not super secret stuff or anything but still a good idea not to annoy our HPE account manager, it's some very important tech for AMD.

a fifth die with a l4 cache would be pretty cool, be it fast low quantity or slower high quantity (hbm)or better yet both

 

22 minutes ago, Taf the Ghost said:

I do think, at best, we'd only ever see 2-die MCM for consumer. Probably with the dies extremely close together, on a new interposer-type technology. (There's a few already coming into use & in the pipeline.) They'd probably do some interesting things to connect the dies, but the IF would probably be the Control Layer rather than the interconnect layer there. Or they find a way to put 10 IF links on a die, haha.

if i am not mistaken IF can be used over whatever they want as its just a protocol, though for that they probably don't want to run it over pcie phys, amd did just patent their own silicon interposer on substrate which is really important to reduce gpu costs, increase die to die connection speeds and might even be useful on the epyc side of things to increase the bandwidth between them 

the 5 die approach could also mean that post processing is done on that die so the stuf we were talking about being hard to do would be fixed

[leadeater]

19 minutes ago, Taf the Ghost said:

IF would probably be the Control Layer rather than the interconnect layer there. Or they find a way to put 10 IF links on a die, haha.

That's the nice thing about IF, it was designed from the start to be a transport protocol that can be used over any transport layer/medium. That's why it works intra die, inter die and inter socket (over PCIe).

[Lurick]

Hopefully, if it's a new EPYC CPU, it won't need a new socket and can just be dropped into existing EPYC servers

 

https://www.zdnet.com/article/cisco-unveils-amd-epyc-powered-servers/

[cj09beira]

anyways all this wont be coming before we leave gcn behind as it would be stupid to invest in it when you have a new thing coming that supposedly is better, though there might be a lot from gcn that will live on on the new stuff, so until then we might be stuck with 64 rops and 64 cus, though that scalability thing still puzzles me 

[Taf the Ghost]

7 minutes ago, leadeater said:

That's the nice thing about IF, it was designed from the start to be a transport protocol that can be used over any transport layer/medium. That's why it works intra die, inter die and inter socket (over PCIe).

Yup. Though AMD has gotten a little annoying as they call everything about Comms "Infinity Fabric" these days, haha. 

2 minutes ago, cj09beira said:

anyways all this wont be coming before we leave gcn behind as it would be stupid to invest in it when you have a new thing coming that supposedly is better, though there might be a lot from gcn that will live on on the new stuff, so until then we might be stuck with 64 rops and 64 cus, though that scalability thing still puzzles me 

2021's Radeon Pro Duo (Navi edition) strikes me as the first time we'd likely to see it. We wouldn't see it on consumer or professional until 2022 with the "refresh" of the new Architecture.

[leadeater]

4 minutes ago, Taf the Ghost said:

Yup. Though AMD has gotten a little annoying as they call everything about Comms "Infinity Fabric" these days, haha. 

So AMD is going to war with Infinity, shall we call it an Infinity War 

Bad jokes ftw.

[Taf the Ghost]

Just now, leadeater said:

So AMD is going to war with Infinity, shall we call it an Infinity War 

Bad jokes ftw.

I think I've only seen one "Lisa Su snaps her fingers" meme joke so far.

[leadeater]

2 minutes ago, VegetableStu said:

and half the AMD team disappears

Shut up shut up shut up, I haven't seen the movie yet lol.

[Misanthrope]

4 hours ago, leadeater said:

Nvidia furnace Fermi? 480 ran as hot as the dual GPU 4870X2 lol.

And you went back how many years to get that example?

 

Look I get it the person you quoted said "always" but at this point since CGN 1.0 AMD has been behind Nvidia in all fronts (including TDP) except compute for so long you can be more charitable in your interpretation of "always" and realize "a good 9 fucking years pushing 10" is for pragmatical terms almost the same as always.

[leadeater]

26 minutes ago, Misanthrope said:

And you went back how many years to get that example?

 

Look I get it the person you quoted said "always" but at this point since CGN 1.0 AMD has been behind Nvidia in all fronts (including TDP) except compute for so long you can be more charitable in your interpretation of "always" and realize "a good 9 fucking years pushing 10" is for pragmatical terms almost the same as always.

Well it's good thing I wasn't really being serious with that example, you'd have to be rather delusional to think AMD has ever really been ahead of Nvidia ever for anything. They had a few generations of being first to a smaller node but that's about it, and that's even further back than this.

[Mira Yurizaki]

3 hours ago, cj09beira said:

amd might need less bandwidth than nvidea depending on the way they go about doing it, for example gcn already divides each frame into quadrants and solves one in each shader engine, they could have each die solve 1 or 2 quarters (depending on the number of dies) of the image and then only need to send the final image to a master to send it to the monitor (after sewing them together), this method unless i am missing something would need little bandwidth at the cost of lots of vram

 

edit:

btw those numbers are at what memory frequency, because i bet IF can be clocked higher in the next iterations 

NVIDIA has already done this since Maxwell, by doing tile-based rendering at the hardware level. This is why they were able to get away with a GPU that performs as good as a GPU that had 150% of the bandwidth. As far as I know, AMD hasn't done this approach yet (or they have, just very recently).

 

See:

 

The thing with AMD is I feel their mantra for GCN has been basically it needs to be a jack-of-all-trades GPU architecture. When NVIDIA made Kepler, they went "game developers don't care about FP64 and raw compute power", focused the compute stuff to where it mattered more, and gave consumers something that was efficient at doing graphics.

[cj09beira]

 

56 minutes ago, Taf the Ghost said:

Yup. Though AMD has gotten a little annoying as they call everything about Comms "Infinity Fabric" these days, haha. 

2021's Radeon Pro Duo (Navi edition) strikes me as the first time we'd likely to see it. We wouldn't see it on consumer or professional until 2022 with the "refresh" of the new Architecture.

if i am not mistaken the new architecture is scheduled for 2020 so it might come earlier than 2022

[JediFragger]

44 minutes ago, leadeater said:

Shut up shut up shut up, I haven't seen the movie yet lol.

You've done *really* well if you've avoided any spoilers so far man!!!

[cj09beira]

11 minutes ago, M.Yurizaki said:

NVIDIA has already done this since Maxwell, by doing tile-based rendering at the hardware level. This is why they were able to get away with a GPU that performs as good as a GPU that had 150% of the bandwidth. As far as I know, AMD hasn't done this approach yet (or they have, just very recently).

we are talking about mcm gpus nothing to do with what you mentioned