AMD to publicily reveal new HW at Computex.

[Mira Yurizaki]

3 minutes ago, cj09beira said:

we are talking about mcm gpus nothing to do with what you mentioned

You were talking about bandwidth requirements and how AMD renders things and bandwidth requirements were a concern back there as far as using an MCM architecture goes because inter-die communication usually isn't as fast as intra-die communication.

 

Ergo, I provided an example of a bandwidth saving technique.

 

Along with some other thoughts that I just tacked on.

[leadeater]

6 minutes ago, M.Yurizaki said:

You were talking about bandwidth requirements and how AMD renders things and bandwidth requirements were a concern back there as far as using an MCM architecture goes because inter-die communication usually isn't as fast as intra-die communication.

 

Ergo, I provided an example of a bandwidth saving technique.

 

Along with some other thoughts that I just tacked on.

I think TBR was supposed to be in Vega but we never really got a clear answer if that was functional or not, Vega being so darn rare no one actually cares anyway.

[Mira Yurizaki]

Just now, leadeater said:

I think TBR was supposed to be in Vega but we never really got a clear answer if that was functional or not, Vega being so darn rare no one actually cares anyway.

It would be nice if that guy who discovered NVIDIA's TBR ran it on recent AMD GPUs, but alas. Then again he posted the code for his program so it's not like someone else can't do it

[cj09beira]

3 minutes ago, M.Yurizaki said:

You were talking about bandwidth requirements and how AMD renders things and bandwidth requirements were a concern back there as far as using an MCM architecture goes because inter-die communication usually isn't as fast as intra-die communication.

 

Ergo, I provided an example of a bandwidth saving technique.

 

Along with some other thoughts that I just tacked on.

except we aren't talking about the same bandwidth here, that only reduces a bit the bandwidth needed for the vram, the bandwidth needed for die to die comunication would still be huge, what i was talking about is basicly have the gpu be more independent of each other and only have to stitch together the frame at the end, this of course would mean more vram needed, 

[cj09beira]

1 minute ago, M.Yurizaki said:

It would be nice if that guy who discovered NVIDIA's TBR ran it on recent AMD GPUs, but alas. Then again he posted the code for his program so it's not like someone else can't do it

if i am not mistaken it was done but the result was the same as other amd cards 

[leadeater]

2 minutes ago, cj09beira said:

except we aren't talking about the same bandwidth here, that only reduces a bit the bandwidth needed for the vram, the bandwidth needed for die to die comunication would still be huge, what i was talking about is basicly have the gpu be more independent of each other and only have to stitch together the frame at the end, this of course would mean more vram needed, 

TBR could be used as the method to split up the rendering across dies since that is done before the actual rendering takes place, you would probably need to have some kind of extra output memory buffer to put the final image in to so you can then pull it back out again for post effects or something. Or maybe you just have memory pointers and mirror to the other memory zones for each die for the render result so they all have a copy and can all do a combine.

[Mira Yurizaki]

2 minutes ago, cj09beira said:

except we aren't talking about the same bandwidth here, that only reduces a bit the bandwidth needed for the vram, the bandwidth needed for die to die comunication would still be huge, what i was talking about is basicly have the gpu be more independent of each other and only have to stitch together the frame at the end, this of course would mean more vram needed, 

Isn't that what SLI/Crossfire does already? The GPUs render things independently and they're only passing rendered frames (or portions of it) to the master GPU for final composition.

[cj09beira]

2 minutes ago, leadeater said:

TBR could be used as the method to split up the rendering across dies since that is done before the actual rendering takes place, you would probably need to have some kind of extra output memory buffer to put the final image in to so you can then pull it back out again for post effects or something. Or maybe you just have memory pointers and mirror to the other memory zones for each die for the render result so they all have a copy and can all do a combine.

that wouldn't be much different from dividing the screen in quadrants the only difference would be that you would divide it diagonally, you would still end up needing loads of vram and stitching would probably become more problematic

[cj09beira]

2 minutes ago, M.Yurizaki said:

Isn't that what SLI/Crossfire does already? The GPUs render things independently and they're only passing rendered frames (or portions of it) to the master GPU for final composition.

no one gpu does one frame completely while the other is doing the next frame

[leadeater]

4 minutes ago, M.Yurizaki said:

Isn't that what SLI/Crossfire does already? The GPUs render things independently and they're only passing rendered frames (or portions of it) to the master GPU for final composition.

Currently they alternate and render entire frames rather than split the frames and render parts of the same frame, slave passes rendered frame back to master directly to output.

[Mira Yurizaki]

1 minute ago, leadeater said:

Currently they alternate and render entire frames rather than split the frames and render parts of the same frame, slave passes rendered frame back to mater directly to output.

 

1 minute ago, cj09beira said:

no one gpu does one frame completely while the other is doing the next frame

Split Mode Rendering has been a thing in SLI since the beginning, but it wasn't really used in practice because of what I presume is the extra effort to make it work well.

 

Source thingy: https://docs.nvidia.com/gameworks/content/technologies/desktop/sli.htm

[leadeater]

Just now, M.Yurizaki said:

Split Mode Rendering has been a thing in SLI since the beginning, but it wasn't really used in practice because of what I presume is the extra effort to make it work well.

 

Source thingy: https://docs.nvidia.com/gameworks/content/technologies/desktop/sli.htm

SFR sort of exists in Crossfire too, it's just not used for the post processing issues I mentioned. You can't guarantee a uniform looking frame using using SFR and post processing.

 

True SFR actually means you get double the VRAM too, it's pooled rather than mirrored but cross accessing the pool is terribly slow.

[Doobeedoo]

Most of what is expected, some additional Ryzen refreshes and Vega that probably won't be for gamers. 

So gap bridge closure products until 7nm Zen2 and Navi next year, which are more exciting though.

[Taf the Ghost]

24 minutes ago, leadeater said:

TBR could be used as the method to split up the rendering across dies since that is done before the actual rendering takes place, you would probably need to have some kind of extra output memory buffer to put the final image in to so you can then pull it back out again for post effects or something. Or maybe you just have memory pointers and mirror to the other memory zones for each die for the render result so they all have a copy and can all do a combine.

The more we talk about this, I really do think this is going to be part of AMD's new full architecture. They'd need a full new pipeline approach to handle MCM for gaming GPUs.

[Mira Yurizaki]

14 minutes ago, leadeater said:

SFR sort of exists in Crossfire too, it's just not used for the post processing issues I mentioned. You can't guarantee a uniform looking frame using using SFR and post processing.

 

True SFR actually means you get double the VRAM too, it's pooled rather than mirrored but cross accessing the pool is terribly slow.

Then we get to making a NUMA based platform for GPUs, which comes with all the fun things NUMA based platforms in CPU land bring.

[Taf the Ghost]

51 minutes ago, cj09beira said:

 

if i am not mistaken the new architecture is scheduled for 2020 so it might come earlier than 2022

Pretty sure last roadmap was "Next Gen" in 2021. But they could also end up releasing it in 2020 if it's ready. If the MCM works for Compute, those really might be out in 2020, but I really do think they're going to be doing a Proof of Concept with a Pro Duo first, with Navi dies. Let's them have full testing before completely committing to that direction.

[Taf the Ghost]

8 minutes ago, M.Yurizaki said:

Then we get to making a NUMA based platform for GPUs, which comes with all the fun things NUMA based platforms in CPU land bring.

The most interesting parts about TR & Epyc might be that almost nothing really cares about NUMA topology. The issues were always that the CPUs used to be several inches away. Given the only task that actually seems bothered about it, in a CPU + GPU situation, is gaming, we're in a weird place because the GPU is a massive parallel operation.

 

I think the biggest challenge is going to be getting even latency across the dies. If they can get that nailed down, the rest is a little easier, and they can bring up the inter-die communication over time. I wonder if they'd do some sort of checkerboard pattern approach. In the theoretical 4 die high-end GPU, that'd split 16 pieces per die, per frame. Or even by however many CUs per. If it was a stack of 32 CU dies, for 128 total CUs, you'd have that many segments to assign. Or a die just renders every 4th frame, lol.

 

Related to this, but with recent chatter about Zen2 designs, a thought struck me. Canard PC had that leak about 16c/32t design, and we're pretty sure that's at TSMC to launch by the end of the year. My thought has been that AMD would do two designs: Big (Server/TR) and Medium (Desktop, high frequency Server). It struck me, given they've moved to a highly modular design approach, that AMD could actually reuse the entire "Big" design, just swap out a CCX for a 6-8 CU Vega iGPU. 16c/32t is too much for AM4 and the dual channel memory, but 12c would work. And moving to all Ryzen 3000 series having an iGPU would let AMD get completely back into the OEM space.

 

 

[cj09beira]

3 minutes ago, Taf the Ghost said:

Related to this, but with recent chatter about Zen2 designs, a thought struck me. Canard PC had that leak about 16c/32t design, and we're pretty sure that's at TSMC to launch by the end of the year. My thought has been that AMD would do two designs: Big (Server/TR) and Medium (Desktop, high frequency Server). It struck me, given they've moved to a highly modular design approach, that AMD could actually reuse the entire "Big" design, just swap out a CCX for a 6-8 CU Vega iGPU. 16c/32t is too much for AM4 and the dual channel memory, but 12c would work. And moving to all Ryzen 3000 series having an iGPU would let AMD get completely back into the OEM space.

 

 

i don't think that will happen especially considering they might do a zen 2 6 core apu, if you need more cores you will most probably also need more gpu, and that would also make the price advantage amd has over intel disappear at least on the consumer space 

[dalekphalm]

9 hours ago, leadeater said:

I don't think they will be able to, not without a bunch of caveats that will spark arguments for the ages i.e. power draw. RTG trying to do things they just can't hurts their rep every time, biggest reason Ryzen got so much hype was consumers and AMD themselves gave up on the notion that they had high end CPUs so stopped trying to act like they did or could until something drastic was done. Just do the same now, stop competing above 1070 tier performance until you can do something drastic then ride that bigger wave not ones that you can't surf because they never break (fyi don't know a damn thing about surfing lol).

While I agree, this is probably the smartest approach for AMD, fanboys and others don't seem to agree.

 

Every single time AMD comes out with just lower end cards to compete (which do compete well) with NVIDIA's low and medium end offerings, people yell and scream and whine that AMD doesn't care about high end users. Or they say "Well look, they can't even keep up with NVIDIA's highest end! Why should I care about their lower end offerings? They must suck!"

 

It's a no-win scenario for AMD until they can get the resources to invest into proper GPU R&D. I suspect they are still at least 12 months away from anything "ground breaking" - but who knows how long that might actually take?

7 hours ago, leadeater said:

Nvidia furnace Fermi? 480 ran as hot as the dual GPU 4870X2 lol.

People conveniently forget that the NVIDIA GTX 400 and 500 series GPU's were hotter than anything AMD has put out. The 480 in particular is renown for it's heat generating capacity.

[JediFragger]

11 minutes ago, dalekphalm said:

People conveniently forget that the NVIDIA GTX 400 and 500 series GPU's were hotter than anything AMD has put out. The 480 in particular is renown for it's heat generating capacity.

But at least nVidia learned from their ways and switched to a more frugal power route. Let's hope AMD can make the same transition.

[Mira Yurizaki]

16 minutes ago, Taf the Ghost said:

Related to this, but with recent chatter about Zen2 designs, a thought struck me. Canard PC had that leak about 16c/32t design, and we're pretty sure that's at TSMC to launch by the end of the year. My thought has been that AMD would do two designs: Big (Server/TR) and Medium (Desktop, high frequency Server). It struck me, given they've moved to a highly modular design approach, that AMD could actually reuse the entire "Big" design, just swap out a CCX for a 6-8 CU Vega iGPU. 16c/32t is too much for AM4 and the dual channel memory, but 12c would work. And moving to all Ryzen 3000 series having an iGPU would let AMD get completely back into the OEM space.

While I believe this approach can work, it presents a problem of how will each GPU node know what to work on. Which means they either have to pair the GPU cluster with a master scheduler or they have to make sure their drivers are really up to snuff.

[dalekphalm]

45 minutes ago, JediFragger said:

But at least nVidia learned from their ways and switched to a more frugal power route. Let's hope AMD can make the same transition.

I think AMD is working their way down that path. But that path takes a lot of R&D money. If AMD has to choose between "making their GPU significantly less hot" vs "making their GPU significantly more powerful", I know which one I'd prefer they focus on. Their GPU's are NOT as hot as the meme's make out. The worst was the RX 290 (Hawaii) running the stock cooler. And that's frankly more to do with a goddamn shit stock cooler than the GPU itself actually running that hot. The aftermarket 290's ran significantly cooler. And the 390 revision all but eliminated the heating issues.

 

AMD also didn't focus on power draw, because, frankly, it was never an issue in the minds of gamers, until NVIDIA said it was an issue. It was like someone flipped a switch. One day, people didn't give a shit about power draw. The next day, they were losing their shit over AMD's "power hungry" GPU's.

 

So there was a massive paradigm shift that happened essentially overnight, started by NVIDIA, and AMD simply missed the boat on that one.

[Trixanity]

54 minutes ago, dalekphalm said:

I think AMD is working their way down that path. But that path takes a lot of R&D money. If AMD has to choose between "making their GPU significantly less hot" vs "making their GPU significantly more powerful", I know which one I'd prefer they focus on. Their GPU's are NOT as hot as the meme's make out. The worst was the RX 290 (Hawaii) running the stock cooler. And that's frankly more to do with a goddamn shit stock cooler than the GPU itself actually running that hot. The aftermarket 290's ran significantly cooler. And the 390 revision all but eliminated the heating issues.

 

AMD also didn't focus on power draw, because, frankly, it was never an issue in the minds of gamers, until NVIDIA said it was an issue. It was like someone flipped a switch. One day, people didn't give a shit about power draw. The next day, they were losing their shit over AMD's "power hungry" GPU's.

 

So there was a massive paradigm shift that happened essentially overnight, started by NVIDIA, and AMD simply missed the boat on that one.

Very true. Probably one of the most brilliant marketing pushes I've seen.

Power was never a serious talking point until it suddenly was. A smart way to differentiate when performance was still similar.

[Humbug]

5 minutes ago, dalekphalm said:

AMD also didn't focus on power draw, because, frankly, it was never an issue in the minds of gamers, until NVIDIA said it was an issue. It was like someone flipped a switch. One day, people didn't give a shit about power draw. The next day, they were losing their shit over AMD's "power hungry" GPU's.

 

So there was a massive paradigm shift that happened essentially overnight, started by NVIDIA, and AMD simply missed the boat on that one.

This is true for the most part. Especially for gamers power bills are not an issue, we only game a short amount of time and only then the GPU is under load.

 

For example I run an Sapphire R9 290 vapor-x.  Fantastic factory overclocked card. Runs fast, cool and quiet. It takes more power than Nvidia's GTX 780 and GTX 970. But it was never an issue. I still run it no sweat along with an i7 3770K, 3 disk drives, a AIO water cooler and lots of case fans all powered by a Seasonic 550 watt gold certified PSU. I can ever overclock the CPU and GPU on this PSU. So power consumption is not an issue, I don't need an monster watt PSU... The same goes for the Fury X, the Vega56 etc.

 

But with the Vega64 I really think AMD created a slightly unbalanced product. This thing takes 100 watts more than the Vega56 for only 10% more performance. All because they wanted to clock it high to match GTX 1080 stock performance. So they went a bit too far outside the optimal point on the curve of performance:power for the vega architecture.

 

If I was them I would have just released one Vega GPU, fully unlocked with all 64 CUs but at Vega56 clocks. It would have performed and priced just under the GTX 1080. Then if users want to remove the power limit and overclock another 200Mhz to surpass the GTX 1080 they still can. But you have a nice balanced stock product with lots of room for the AIBs to play around...

[dalekphalm]

2 minutes ago, Trixanity said:

Very true. Probably one of the most brilliant marketing pushes I've seen.

Power was never a serious talking point until it suddenly was. A smart way to differentiate when performance was still similar.

Agreed - NVIDIA has always been better at marketing. I don't know why, exactly. A better team perhaps? But even when they give the same message, and have the same results, gamers tend to believe NVIDIA more than AMD.