AMD confirms Q1 2018 release for next-generation Ryzen 2000 series processors

[Taf the Ghost]

@cj09beira It's pure speculation on my part, but a lot of moves can be sorted out by simply putting yourself in the assumption of the parties making the decisions. The design split is needed, but AMD can leverage both designs across both major products as well.

[RagnarokDel]

I really hope I can use my R7 1700 on the new chipset so that I can upgrade to Zen2 in 2019 all using the same chipset. (I'm disappointed with my mobo, basically)

[cj09beira]

20 minutes ago, Taf the Ghost said:

@cj09beira It's pure speculation on my part, but a lot of moves can be sorted out by simply putting yourself in the assumption of the parties making the decisions. The design split is needed, but AMD can leverage both designs across both major products as well.

i totally agree that they will make 2 dies with different core counts, just dont know what the core counts will be, 

[cj09beira]

22 minutes ago, RagnarokDel said:

I really hope I can use my R7 1700 on the new chipset so that I can upgrade to Zen2 in 2019 all using the same chipset. (I'm disappointed with my mobo, basically)

which board did you got?

[linustouchtips]

last generation was so yesterday here comes the refresh oh yea was i a beta tester maybe

[Jito463]

7 hours ago, Taf the Ghost said:

Well, getting the full stack of the current one out to Market would help. Epyc and Skylake-SP have been really slow to roll out.

To be fair, server parts aren't something you want rushed to market.  If they're going to be used in a server, you want to be sure they've been thoroughly tested and validated.

[leadeater]

7 hours ago, cj09beira said:

i totally agree that they will make 2 dies with different core counts, just dont know what the core counts will be, 

I don't think we are going to see any changes to die and/or CCX configurations until Zen 2 and even then I'm not too sure about a divergence of CCX configuration between server and desktop. I wouldn't be surprised to see die differences outside of the CCX but I can't really see much benefit to making say 4 core CCXs for desktop and 6 core CCX for server. wouldn't save much in fabrication cost and would add a significant cost to design and fabrication preparation.

 

Maybe if AMD ditched CCXs (only used 1) on the desktop side but then that removes the architectural benefits from doing it, defects have less chance ruining an entire die and power control and efficiency to name two.

 

Say they went to 6 core CCXs, you can by product stack always disable 2 cores in each to increase the power per core to allow high frequencies then on the server line have them enabled. It would also allow for more dies to be salvaged in to usable parts too.

 

I think it would be a big mistake to separate the product stacks like Intel does, what if you wanted a much cheaper development workstation and needed AVX-512 and the full version of it not the limited one Intel is giving the desktop chips. Having common architecture and features across all products is actually highly appealing to me and won't force people to buy products they don't need.

[Taf the Ghost]

7 hours ago, leadeater said:

I don't think we are going to see any changes to die and/or CCX configurations until Zen 2 and even then I'm not too sure about a divergence of CCX configuration between server and desktop. I wouldn't be surprised to see die differences outside of the CCX but I can't really see much benefit to making say 4 core CCXs for desktop and 6 core CCX for server. wouldn't save much in fabrication cost and would add a significant cost to design and fabrication preparation.

 

Maybe if AMD ditched CCXs (only used 1) on the desktop side but then that removes the architectural benefits from doing it, defects have less chance ruining an entire die and power control and efficiency to name two.

 

Say they went to 6 core CCXs, you can by product stack always disable 2 cores in each to increase the power per core to allow high frequencies then on the server line have them enabled. It would also allow for more dies to be salvaged in to usable parts too.

 

I think it would be a big mistake to separate the product stacks like Intel does, what if you wanted a much cheaper development workstation and needed AVX-512 and the full version of it not the limited one Intel is giving the desktop chips. Having common architecture and features across all products is actually highly appealing to me and won't force people to buy products they don't need.

Somewhere this thread became about us discussing what was coming with Zen2. Anyway, my expectation, given the stated aspects of the Zen design philosophy, is that they're going to share the actual core designs between all of their branches. Then, in each generation, the CCX will be identical. After that, they can branch wherever they need to.

 

Zen2 should be 4c per CCX. I think Zen3, with the area shrink of a refined node, is where we get a larger CCX. Either 6c or 8c. 6c probably makes the most sense from what little information we have right now, but we'll hear about it in 18 months. AMD will need some of the deeper testing with the 16mb L3 cache to see if going up in cores per CCX causes bottlenecks.

 

But Zen2 will almost assuredly have much better AVX2 support, which should help AVX512 as well. (Though, since Intel hasn't even fully rolled out the AVX512 instruction sets, are we sure it's that important for AMD for now? Some of this can clearly wait until Zen3 for the simple fact that AMD doesn't have to push that tech, Intel does.)

[leadeater]

Just now, Taf the Ghost said:

Zen2 should be 4c per CCX. I think Zen3, with the area shrink of a refined node, is where we get a larger CCX

Zen+ = Ryzen 2

Zen2 = Ryzen 3

 

Don't blame me for the confusing names . I always talk architectures anyway since those mean exactly what they are and don't get changed from awesome names like Naples to EPYC (bleeeehhhh).

 

I expect very little to change with Zen+ and with the roll-out of EPYC being so slow it makes it hard for me to see what AMD might want to do with Zen2. AVX gets banded around a lot as some critically important feature but really it isn't, not for the 80% of people out there but it's one of those features that sells a product due to benchmarks.

 

If AMD wants in on the server compute market in the research space they are going to need AVX512, no question there as with each iteration of AVX it becomes a requirement to have it to get those customers. That doesn't mean AMD can't be in on the game for these customers, AMD EPYC actually looks like it would make excellent storage nodes for things like Ceph due to high core counts and PCIe lanes as well as being cheaper than an Intel system for the same purpose.

 

With a die shrink for Zen2 it makes a lot of sense to add AVX-512 then if they are going to be making improvements in that area, seems like a wasted opportunity to just improve AVX2 when for the people that rely on it would be switching to AVX-512. However I put the likelihood of it rather low.

 

If I were to place bets:

• Zen+: Improved clocks and memory controller, minor tweaks to Infinity Fabric
• Zen2: 6 core CCX, 2 core XFR and improved turbo tables, full AVX2, improved memory controller, PCIe 4.0
• Zen3: Likely too far off to say much here but, AVX-512 and 4 socket support (due to PCIe 4.0)

[Taf the Ghost]

1 hour ago, leadeater said:

Zen+ = Ryzen 2

Zen2 = Ryzen 3

 

Don't blame me for the confusing names . I always talk architectures anyway since those mean exactly what they are and don't get changed from awesome names like Naples to EPYC (bleeeehhhh).

 

I expect very little to change with Zen+ and with the roll-out of EPYC being so slow it makes it hard for me to see what AMD might want to do with Zen2. AVX gets banded around a lot as some critically important feature but really it isn't, not for the 80% of people out there but it's one of those features that sells a product due to benchmarks.

 

If AMD wants in on the server compute market in the research space they are going to need AVX512, no question there as with each iteration of AVX it becomes a requirement to have it to get those customers. That doesn't mean AMD can't be in on the game for these customers, AMD EPYC actually looks like it would make excellent storage nodes for things like Ceph due to high core counts and PCIe lanes as well as being cheaper than an Intel system for the same purpose.

 

With a die shrink for Zen2 it makes a lot of sense to add AVX-512 then if they are going to be making improvements in that area, seems like a wasted opportunity to just improve AVX2 when for the people that rely on it would be switching to AVX-512. However I put the likelihood of it rather low.

 

If I were to place bets:

• Zen+: Improved clocks and memory controller, minor tweaks to Infinity Fabric
• Zen2: 6 core CCX, 2 core XFR and improved turbo tables, full AVX2, improved memory controller, PCIe 4.0
• Zen3: Likely too far off to say much here but, AVX-512 and 4 socket support (due to PCIe 4.0)

Haha. I try to stick to uArchs as well. 

 

Zen+: 8-15% higher clocks; 1-5% IPC gain just from IF and IMC tweaks; 3600 Mhz memory pretty much a given.

Zen2: 4c CCX; 2 CCX Mainstream & 4 CCX Server splits; double the AVX2 units and some parts of AVX512; PCIe 4.0

Zen3: 6c CCX; DDR5

 

I should note there's a chance a Zen2+ will happen in 2020 if DDR5 is really late. It'd be something like what is happening with Zen+ right now, but it's not impossible that both AMD & Intel are both forced to refresh for a full year because DDR5 is really late.

[Eduard the weeb]

AHHHHH I just wanted to buy the R7 1700 and now I have to wait up to 3 months to build or upgrade later.

[leadeater]

17 minutes ago, Taf the Ghost said:

Zen+: 8-15% higher clocks; 1-5% IPC gain just from IF and IMC tweaks; 3600 Mhz memory pretty much a given.

Zen2: 4c CCX; 2 CCX Mainstream & 4 CCX Server splits; double the AVX2 units and some parts of AVX512; PCIe 4.0

Zen3: 6c CCX; DDR5

Not sure why you wouldn't increase core count in Zen2 but increase it in Zen3 when both are supposed to use same node size.

 

4 CCX could be a thing but I'd like to see much more performance tests and real world impressions of performance before I'd say that is a good thing, more NUMA nodes is a bad thing if optimization hasn't even been done for 2 CCXs.

 

Edit:

Oh and that big of a jump in cores per die is really going to put a bottleneck on ram speed to those cores. Only got dual channel to service potentially 16 cores, 8 channels over the whole CPU but a single core doesn't have access to all 8, Intel's mesh is superior in that regard as they still implement core groups to an IMC each side of the die but they can still access the non primary IMC without a huge latency and bandwidth penalty like with AMD. 

 

Edit 2:

Have a look at the '8 threads on the first 8 cores same socket' and '4 threads on the first 4 cores same socket' figures for EYPC and Skylake-SP/Broadwell-EP

https://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd-epyc-7000-cpu-battle-of-the-decade/12

[Taf the Ghost]

48 minutes ago, leadeater said:

Not sure why you wouldn't increase core count in Zen2 but increase it in Zen3 when both are supposed to use same node size.

 

4 CCX could be a thing but I'd like to see much more performance tests and real world impressions of performance before I'd say that is a good thing, more NUMA nodes is a bad thing if optimization hasn't even been done for 2 CCXs.

 

Edit:

Oh and that big of a jump in cores per die is really going to put a bottleneck on ram speed to those cores. Only got dual channel to service potentially 16 cores, 8 channels over the whole CPU but a single core doesn't have access to all 8, Intel's mesh is superior in that regard as they still implement core groups to an IMC each side of the die but they can still access the non primary IMC without a huge latency and bandwidth penalty like with AMD. 

 

Edit 2:

Have a look at the '8 threads on the first 8 cores same socket' and '4 threads on the first 4 cores same socket' figures for EYPC and Skylake-SP/Broadwell-EP

https://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd-epyc-7000-cpu-battle-of-the-decade/12

Zen3 is supposed to be on the refined 7nm process, so likely a small area shrink and/or improved yields. That's when you can start stuffing more cores onto the CCX, which goes with your point about memory bandwidth to the CCX. Zen3 should be using DDR5, which will greatly improve the bandwidth available, which is a good time to improve the needed bandwidth for that CCX approach.

 

We have the one leak about 16c design for Zen2, which is why I feel that's AMD's Server design. 48c/96t part was on their Roadmap as far back as 2015, so AMD has been planning to either increase the CCX size or add more CCX to Zen2. We'll find out next year, but the 16c Server part could be somewhat memory starved in specific approaches. Though maybe AMD has found a way around that issue.

[leadeater]

Just now, Taf the Ghost said:

We have the one leak about 16c design for Zen2, which is why I feel that's AMD's Server design. 48c/96t part was on their Roadmap as far back as 2015, so AMD has been planning to either increase the CCX size or add more CCX to Zen2.

My guess for a CPU with that configuration it'll be 4 dies, 2 CCXs and 6 cores per CCX which is most similar to it is now, least architectural change and with an improved IMC won't decrease the memory bandwidth per core.

[Taf the Ghost]

6 minutes ago, leadeater said:

My guess for a CPU with that configuration it'll be 4 dies, 2 CCXs and 6 cores per CCX which is most similar to it is now, least architectural change and with an improved IMC won't decrease the memory bandwidth per core.

I've got no insider information, so we'll see. Since some of the hyper-technicals are just far beyond my time to invest in studying them, it's possible they could actually run disabled CCX parts in the Mainstream. As in, they really are only using 1 Design and they're just disable CCXs for each product tier. It the design is small enough, it'd work. Also be a tad nutty.