AMD suggests 16NM finfet chiprs aren't comming in 2015

[cesrai]

One question, what's a chipr?

I don't know put probably some thing that is fast and light.

[spartaman64]

Zen is going to be an APU... Don't know why you people think it will be a dedicated CPU like the FX series. Even Intel is dumping socket 2011 with Skylake. Everything is going iGPU for heterogeneous acceleration.

what i thought carrzo was going to be the apu and zen is going be the new fx cpu

[Ren]

To be fair, Intel isn't exactly providing great products. I don't think a delay or chance of plans affects much..

[patrickjp93]

Didn't they already drop 2011?

2011-3 was moving pins around, but it's the same mounting points and everything else.

[patrickjp93]

Already surpassed Sandy Bridge's process node. Sandy Bridge was on 32 nm and Kaveri is on 28 nm.

In performance, and no, AMD's 28nm process and Intel's 32 are equivalent. Intel released a white paper on that a long time ago. The shrink from 32 to 28 gained AMD almost nothing.

[patrickjp93]

I'm even more excited to see how well Excavator performs. With the use of HDL its equivalent to a full process node improvement. So easily 15-30% increase in performance per watt. Hopefully Carrizo makes it to the desktop and overclocking isn't hindered by HDL. Otherwise AMD might break Sandy Bridge IPC waters easily this time around.

Facepalm* HDL weakens clock rates for the sake of very fast design. A computer more or less designed Carrizo. Please look shit up before you make these assumptions. AMD gained IPC for another 400MHz clock rate loss.

[fringie]

So, we're still getting 20nm GPU's next year..? I was about to freak out >.>. 

[patrickjp93]

what i thought carrzo was going to be the apu and zen is going be the new fx cpu

No, Carrizo is the end of the bulldozer architecture line (Excavator cores). We might see an Excavator-based FX chip just as we saw the steamroller refresh with the 8370/E/XE a few months ago.

There MIGHT be a Zen-based FX chip, but AMD is fully invested in HSA, and the whole world is moving towards heterogeneous solutions. To expect a Zen-based FX chip is a bit foolhardy at this point.

[KeltonDSMer]

 We might see an Excavator-based FX chip just as we saw the steamroller refresh with the 8370/E/XE a few months ago.

 

 

Those chips are still piledriver, not excavator like 860k/7850k. According to AMD's road maps there will not be any fx refresh until zen (if they decide to reuse the fx moniker).

[Opcode]

In performance, and no, AMD's 28nm process and Intel's 32 are equivalent. Intel released a white paper on that a long time ago. The shrink from 32 to 28 gained AMD almost nothing.

Really now? Kaveri is 245 mm with 2.41 billion transistors meanwhile Sandy Bridge is 216 mm with 995 million transistors. AMD was capable of stuffing nearly twice as many transistors within the same size die.

 

Facepalm* HDL weakens clock rates for the sake of very fast design. A computer more or less designed Carrizo. Please look shit up before you make these assumptions. AMD gained IPC for another 400MHz clock rate loss.

Not at all. HDL is used to essentially compress the architecture to provide performance per watt improvements. It hinders higher base frequencies but the trade off cannot be calculated as neither bad nor good right now. Honestly who cares if Carrizo launches for the desktop at a measly 3.3 GHz or something along them lines. The jump in IPC will still put it a bit ahead of Kaveri offerings out of the box and will at least start to match Intel's general clock range. With that in mind if HDL doesn't hinder overclocking we will see a chip that may blow past Sandy Bridge at a fraction of the cost. The Athlon x4 960k would be the ultimate gamer sweet spot and would knock the G3258 off the scoreboard.

 

No, Carrizo is the end of the bulldozer architecture line (Excavator cores). We might see an Excavator-based FX chip just as we saw the steamroller refresh with the 8370/E/XE a few months ago.

There MIGHT be a Zen-based Fx chip, but AMD is fully invested in HSA, and the whole world is moving towards heterogeneous solutions. To expect a Zen-based FX chip is a bit foolhardy at this point.

The FX-8370E and FX-8320E are still Piledriver just with an updated resonant clock mesh.

[Swndlr]

i would love to see new apu's, but ffs amd hurry with with 300x cards already.

[patrickjp93]

Those chips are still piledriver, not excavator like 860k/7850k. According to AMD's road maps there will not be any fx refresh until zen (if they decide to reuse the fx moniker).

Weird, I though the 8370 had moved up to steamroller... AMD be stoopid...

[UnknownResident]

So, we're still getting 20nm GPU's next year..? I was about to freak out >.>. 

Yeah this should have no effect on 20nm GPUs

[patrickjp93]

Really now? Kaveri is 245 mm with 2.41 billion transistors meanwhile Sandy Bridge is 216 mm with 995 million transistors. AMD was capable of stuffing nearly twice as many transistors within the same size die.

 

Not at all. HDL is used to essentially compress the architecture to provide performance per watt improvements. It hinders higher base frequencies but the trade off cannot be calculated as neither bad nor good right now. Honestly who cares if Carrizo launches for the desktop at a measly 3.3 GHz or something along them lines. The jump in IPC will still put it a bit ahead of Kaveri offerings out of the box and will at least start to match Intel's general clock range. With that in mind if HDL doesn't hinder overclocking we will see a chip that may blow past Sandy Bridge at a fraction of the cost. The Athlon x4 960k would be the ultimate gamer sweet spot and would knock the G3258 off the scoreboard.

 

The FX-8370E and FX-8320E are still Piledriver just with an updated resonant clock mesh.

Did you take the transistor counts of 1 sandy core and 4 kaveri cores or something? You're flat wrong. 

http://en.wikipedia.org/wiki/Transistor_count 2.27 billion.

[Opcode]

Did you take the transistor counts of 1 sandy core and 4 kaveri cores or something? You're flat wrong. 

http://en.wikipedia.org/wiki/Transistor_count 2.27 billion.

If you want to compare 8 core Xeons to quad core Kaveri's. I mean really look at that massive die size 434 mm² for just 2.27 Billion transistors.

 

This is one example as to why serial processing is a thing of the past.

[patrickjp93]

If you want to compare 8 core Xeons to quad core Kaveri's. I mean really look at that massive die size 434 mm² for just 2.27 Billion transistors.

 

This is one example as to why serial processing is a thing of the past.

Okay, so let's go octa-core Vishera (Piledriver) vs 4-Core Sandy. Please note AMD's actual density is way less! Only for Bulldozer v1 (Trinity) did AMD reach density parity with Sandy, and at that point Intel was jumping to 22nm with IB.

http://www.anandtech.com/show/7003/the-haswell-review-intel-core-i74770k-i54560k-tested/5

 

And that's still not taking into account the performance/transistor advantage Intel maintains.

 

Oddly enough, AMD does have higher density between Kaveri and Haswell and a MUCH higher transistor count

http://www.anandtech.com/show/7677/amd-kaveri-review-a8-7600-a10-7850k/4

9.387 million transistors per sq mm for flagship Kaveri

http://www.overclockers.com/intel-i7-4790k-devils-canyon-cpu-review

7.910 million transistors per sq mm for flagship mainstream Intel.

http://www.overclockersclub.com/reviews/iintel_core_i7_5960x_extreme_edition/

7.313 million transistors per sq mm for flagship extreme intel CPU.

 

Now if only AMD could make those transistors do more work...

[Opcode]

Okay, so let's go octa-core Vishera (Piledriver) vs 4-Core Sandy. Please note AMD's actual density is way less!

http://www.anandtech.com/show/7003/the-haswell-review-intel-core-i74770k-i54560k-tested/5

I would leave enthusiast chips such as FX and 2011 out of the comparison as that's not where the market is going (even you've made that claim). When you compare Ivy Bridge on the 22 nm node with GT2 you still only get 7.5 million transistors per mm² in comparison to Kaveri on 28 nm that has 9.8 million transistors per mm². It just goes to show you AMD's ultimately better at making use of die space (even more so with Carrizo). Manufacturing node really means nothing as AMD is still bring forth ground breaking power consumption improvements without even a node change. Intel seems to rely on node improvements for improving their power consumption. Mark my words once AMD gets down to possibly 16 nm FinFET in 2016 their performance per watt is going to be quite impressive. Tho throw a little gas on the fire in regards to this thread sources point to K12 being manufactured on FinFET. So I wouldn't ultimately declare AMD sticking to 28 nm entirely as I presume they will launch a variety of different chips on different nodes.

 

I don't care, a smaller process node isn't going to increase IPC by any means

Die shrinks due to smaller process nodes does in fact boost IPC. Each die shrink boosts IPC usually ~5% and ~10% at best. Now you can imagine if AMD jumped down from 28 nm with Excavator straight to 16 nm. We would see a Bulldozer based architecture that would in fact nearly compete with Haswell.

[patrickjp93]

I would leave enthusiast chips such as FX and 2011 out of the comparison as that's not where the market is going (even you've made that claim). When you compare Ivy Bridge on the 22 nm node with GT2 you still only get 7.5 million transistors per mm² in comparison to Kaveri on 28 nm that has 9.8 million transistors per mm². It just goes to show you AMD's ultimately better at making use of die space (even more so with Carrizo). Manufacturing node really means nothing as AMD is still bring forth ground breaking power consumption improvements without even a node change. Intel seems to rely on node improvements for improving their power consumption. Mark my words once AMD gets down to possibly 16 nm FinFET in 2016 their performance per watt is going to be quite impressive. Tho throw a little gas on the fire in regards to this thread sources point to K12 being manufactured on FinFET. So I wouldn't ultimately declare AMD sticking to 28 nm entirely as I presume they will launch a variety of different chips on different nodes.

 

Die shrinks due to smaller process nodes does in fact boost IPC. Each die shrink boosts IPC usually ~5% and ~10% at best. Now you can imagine if AMD jumped down from 28 nm with Excavator straight to 16 nm. We would see a Bulldozer based architecture that would in fact nearly compete with Haswell.

No, it really wouldn't. AMD's FPU is still 8 clock cycles for a FP multiply/divide. Haswell's is 5, and Broadwell's is 3. AMD still can't touch Sandybridge. When more definitive Carrizo benches come out, I might revise, but until then even Kaveri can't compete unless you;re doing an OpenCL-accelerated task, something Sandybridge's iGPU didn't support at all. Also, I editted my post. 

 

It's actually extremely pathetic that AMD has MUCH higher density and transistor counts in its chips yet still can't match Intel for performance. It's laughable!

[Opcode]

No, it really wouldn't. AMD's FPU is still 8 clock cycles for a FP multiply/divide. Haswell's is 5, and Broadwell's is 3. AMD still can't touch Sandybridge. When more definitive Carrizo benches come out, I might revise, but until then even Kaveri can't compete unless you;re doing an OpenCL-accelerated task, something Sandybridge's iGPU didn't support at all. Also, I editted my post. 

 

It's actually extremely pathetic that AMD has MUCH higher density and transistor counts in its chips yet still can't match Intel for performance. It's laughable!

FPU performance is pretty much irrelevant as their shared FlexFPU is quite powerful for having to withstand twice as many queues. Certainly it's not as fast as each core having their own dedicated FPU but it gets the job done. Any major floating point operations should really be done via the iGPU. Tho this will change with Zen as AMD is going back to a SMT model so each core should have its own FPU once again. What matters is integer performance as that's what ultimately defines general software performance. In all of the desktop software that I have ever written I have never dealt with floating point calculations internally. That's because floating point calculations are primarily found in games and graphical software when you're dealing with multiple dimensions. If Excavator was manufactured on 16 nm FinFET it would give Intel a run for their money especially if there were eight core FX variants of it. Add 15-30% IPC in architecture improvements on top of another easy 10-20% increase in IPC due to the die shrink. That would put the Athlon x4 960k easily in Ivy Bridge/Haswell waters. Certainly it's not going to be as fast as Intel's offerings due to the modular design tho single thread performance would be about on par (which is the biggest complaint). In which case if node costs don't drive up the MSRP having a quad core Athlon that can match a i5-4670k in single thread performance at say $120 would be beyond a huge success for AMD.

[patrickjp93]

FPU performance is pretty much irrelevant as their shared FlexFPU is quite powerful for having to withstand twice as many queues. Certainly it's not as fast as each core having their own dedicated FPU but it gets the job done. Any major floating point operations should really be done via the iGPU. Tho this will change with Zen as AMD is going back to a SMT model so each core should have its own FPU once again. What matters is integer performance as that's what ultimately defines general software performance. In all of the desktop software that I have ever written I have never dealt with floating point calculations internally. That's because floating point calculations are primarily found in games and graphical software when you're dealing with multiple dimensions. If Excavator was manufactured on 16 nm FinFET it would give Intel a run for their money especially if there were eight core FX variants of it. Add 15-30% IPC in architecture improvements on top of another easy 10-20% increase in IPC due to the die shrink. That would put the Athlon x4 960k easily in Ivy Bridge/Haswell waters. Certainly it's not going to be as fast as Intel's offerings due to the modular design tho single thread performance would be about on par (which is the biggest complaint). In which case if node costs don't drive up the MSRP having a quad core Athlon that can match a i5-4670k in single thread performance at say $120 would be beyond a huge success for AMD.

Intel is still king in integer performance too, and if you need branch prediction for your floating point loads (most of the time) then the CPU will be better under a lot of circumstances. It's only when you have truly embarrassingly parallel problems that GPU acceleration shines. That's why so much of software is being experimented with to see if portions can be reduced to such instances. Furthermore, if Integer was King Intel would be pushing for more parallel integer instructions. It's not MMX stayed on 128-bit while SSE and AVX have moved up to 256-bit and now 512-bit for Skylake, or 16 32-bit floats morphed in a single instruction in only 3 cycles.

 

The die shrink is not going to provide 10% on its own. You greatly exaggerate the benefits of HDL as a development choice and Excavator as an architecture. AMD has been saying for a long time Bulldozer and its children are all abysmal failures. If they weren't Keller wouldn't be in the picture now. Also, no, it'd still be under sandybridge. You forget Intel is still working with 4 ALU clusters per core vs. AMD's 2. Sandy and Ivy had 3 per core.

 

Skylake is going to mean a big performance increase as long as software is compiled to take advantage of all system resources available. This is why I stopped developing with G++ and Clang. Intel's compiler is far superior, and you can mod it to use a different dispatcher so that it doesn't hamstring AMD's performance. 

 

That aside though, until AMD catches up to Sandybridge, there's nothing to talk about besides the iGPU wars, and Intel has caught up in compute, caught up in open standards, and is set to crush Carrizo in compute with Iris Pro 6200. Since Carrizo is not coming with HBM, Intel will maintain the bandwidth advantage while keeping costs even by implementing only 64MB of LLC for desktop/server chips, and since AMD will be offering nothing new other than a proprietary programming paradigm (HSA) with Carrizo and a decent but ineffectual IPC increase, Intel will carry that momentum into Skylake and Cannonlake where I suspect they're going to match if not beat AMD in game performance too.

 

At this point whether or not Qualcomm, Arm, Nvidia, and AMD can force Intel's hand to move to HSA in addition to OpenCL 2.x we can only guess, and due to Intel's market dominance, I'm guessing no. Zen is AMD's last real chance or they're going to fall by the wayside. Maybe Samsung or Qualcomm will buy them up and we can see enough money and resources flow back into AMD's R&D to make them competitive again.

[Opcode]

Intel is still king in integer performance too, and if you need branch prediction for your floating point loads (most of the time) then the CPU will be better under a lot of circumstances. It's only when you have truly embarrassingly parallel problems that GPU acceleration shines. That's why so much of software is being experimented with to see if portions can be reduced to such instances. Furthermore, if Integer was King Intel would be pushing for more parallel integer instructions. It's not MMX stayed on 128-bit while SSE and AVX have moved up to 256-bit and now 512-bit for Skylake, or 16 32-bit floats morphed in a single instruction in only 3 cycles.

 

The die shrink is not going to provide 10% on its own. You greatly exaggerate the benefits of HDL as a development choice and Excavator as an architecture. AMD has been saying for a long time Bulldozer and its children are all abysmal failures. If they weren't Keller wouldn't be in the picture now. Also, no, it'd still be under sandybridge. You forget Intel is still working with 4 ALU clusters per core vs. AMD's 2. Sandy and Ivy had 3 per core.

 

Skylake is going to mean a big performance increase as long as software is compiled to take advantage of all system resources available. This is why I stopped developing with G++ and Clang. Intel's compiler is far superior, and you can mod it to use a different dispatcher so that it doesn't hamstring AMD's performance. 

 

That aside though, until AMD catches up to Sandybridge, there's nothing to talk about besides the iGPU wars, and Intel has caught up in compute, caught up in open standards, and is set to crush Carrizo in compute with Iris Pro 6200. Since Carrizo is not coming with HBM, Intel will maintain the bandwidth advantage while keeping costs even by implementing only 64MB of LLC for desktop/server chips, and since AMD will be offering nothing new other than a proprietary programming paradigm (HSA) with Carrizo and a decent but ineffectual IPC increase, Intel will carry that momentum into Skylake and Cannonlake where I suspect they're going to match if not beat AMD in game performance too.

 

At this point whether or not Qualcomm, Arm, Nvidia, and AMD can force Intel's hand to move to HSA in addition to OpenCL 2.x we can only guess, and due to Intel's market dominance, I'm guessing no. Zen is AMD's last real chance or they're going to fall by the wayside. Maybe Samsung or Qualcomm will buy them up and we can see enough money and resources flow back into AMD's R&D to make them competitive again.

Die shrinks do provide ~5% increase in IPC roughly each jump in node. I don't need to exaggerate the benefits of HDL as it's equivalent to a full process node improvement.

 

Everything else in your post is so spotty conforming a reply for it is just unconventional. If you wish to relate to my previous post with a well rounded reply then I will carry on this debate with you.

[patrickjp93]

Die shrinks do provide ~5% increase in IPC roughly each jump in node. I don't need to exaggerate the benefits of HDL as it's equivalent to a full process node improvement.

 

Everything else in your post is so spotty conforming a reply for it is just unconventional. If you wish to relate to my previous post with a well rounded reply then I will carry on this debate with you.

Try to prove the first instead of claiming it. As one who has sat through computer engineering courses, HDL is used to speed up the design process. You lose IPC in the end, whereas a hand-drawn human design can be better optimized. There's no gain in density just for using it. You can always do better than the machine which was built on finite rules. (to the guy who's going to come in here raving about compilers and assembly language programming, you already have the best computer scientists in the world designing compilers. YOU are not going to out-fox them.)

 

The reply is multi-faceted between facts and opinions. Let's start with the first 2 chunks. Everything after was opinion based on the existing marketplace.

[Deletive]

If APU's are 28nm there is a huge gap compared to what Intel has to play it and what AMD has.

28nm to 20nm is a 28.6% decrease.
20nm to 14nm is a 30% decrease.

 

Other then the fact that AMD's CPU performance is lacking; their GPU side of things still manage to work some good performance out of them dispite having a fair amount less of "workable" space for these chips.

 

[Opcode]

Try to prove the first instead of claiming it. As one who has sat through computer engineering courses, HDL is used to speed up the design process. You lose IPC in the end, whereas a hand-drawn human design can be better optimized. There's no gain in density just for using it. You can always do better than the machine which was built on finite rules. (to the guy who's going to come in here raving about compilers and assembly language programming, you already have the best computer scientists in the world designing compilers. YOU are not going to out-fox them.)

 

The reply is multi-faceted between facts and opinions. Let's start with the first 2 chunks. Everything after was opinion based on the existing marketplace.

Your perception on HDL is completely misled. It's not used to speed up the design process it's designed to reduce both area and power consumption. AMD even officially states it being equivalent to a full node improvement in one of their older slides. While the concept is rumored to hinder high frequencies you should still gain the same IPC node improvements (shorter circuit).

 

 

AMD has already officially stated that Excavator cores were shrunken down by 23% from Steamroller with a 40% power consumption reduction. To throw even more into our previous discussion (since Carrizo is being mentioned) Carrizo is 244.62 mm² with 3.1 billion transistors on 28 nm. That's a whopping 12.6 million transistors per mm². AMD is quite good a maximizing utilization of die space and proves you don't need to follow the trend of using smaller nodes to reduce power consumption. Even if AMD does stay on 28 nm with Zen it's not going to hold them back from competing with Intel on a performance per watt basis. Which could prove disastrous for Intel if AMD can manage to get Zen to consume less power than Skylake on a much higher node.

[patrickjp93]

If APU's are 28nm there is a huge gap compared to what Intel has to play it and what AMD has.

28nm to 20nm is a 28.6% decrease.

20nm to 14nm is a 30% decrease.

 

Other then the fact that AMD's CPU performance is lacking; their GPU side of things still manage to work some good performance out of them dispite having a fair amount less of "workable" space for these chips.

 

What's very interesting if you look above is AMD actually has the overall density and transistor count advantage by good margins. It just doesn't seem to be able to make that greater transistor count do as much work as Intel's.