It's a bird, it's a plane, it's...UltraRAM - New experimental NAND that can do literally everything

[BachChain]

Summary

 

Tech startup QuInAsQu has unveiled a working prototype of their "UltraRam" NAND technology. Claimed features include:

• Less than 1ns write latency
• Over ten million write cycle durability
• Non-volatility with data retention estimated at over a thousand years
• Orders of magnitude lower power consumption than existing DRAM

 

Quotes

Quote

UltraRAM is a charge-based memory that uses a floating gate, like flash NAND. Also like flash, the charge state of the floating gate is read non-destructively by measuring the conductance of an underlying ‘channel.’ However, unlike flash, UltraRAM doesn't wear during program and erase cycles because of its TBRT structure. 

 

This is a major qualifier for the durability claims of 10 million write/erase cycles, and the researchers behind UltraRAM are confident enough to claim future testing is expected to see this durability estimate revised upwards. Meanwhile, mainstream TLC 3D NAND might see gate degradation after a few thousand writes.

Quote

The benefits are claimed to include UltraRAM’s 100x lower switching energy than DRAM on the same node (1,000x lower than NAND). Moreover, the UltraRAM researchers asserted that the new memory tech is expected to be capable of 1ns write operations, which is about 10x faster than DRAM.

 

My thoughts

Jeez, does it also give massages? At least they have a working prototype, so it's theoretically not complete BS.

 

Sources

https://www.tomshardware.com/news/ultraram-demos-prototype-chip-secures-funding-to-validate-commercial-potential

[Agall]

14 minutes ago, BachChain said:

Summary

 

Tech startup QuInAsQu has unveiled a working prototype of their "UltraRam" NAND technology. Claimed features include:

• Sub 0.1ns write latency
• ten million write cycle durability
• Non-volatility with thousand-year-plus data retention
• Orders of magnitude lower power consumption

 

Quotes

 

My thoughts

Jeez, does it also give massages? At least they have a working prototype, so it's theoretically not complete BS.

 

Sources

https://www.tomshardware.com/news/ultraram-demos-prototype-chip-secures-funding-to-validate-commercial-potential

Don't see any mention of capacity, probably for a reason.

[Crunchy Dragon]

1 minute ago, Agall said:

Don't see any mention of capacity, probably for a reason.

Give it a decade, we might start seeing DIMM kits of 2x2GB featuring this stuff for just $200!

[Agall]

2 minutes ago, Crunchy Dragon said:

Give it a decade, we might start seeing DIMM kits of 2x2GB featuring this stuff for just $200!

I'm going to guess it's in the metric of MB, which doesn't mean it's useless even now. Having your OS built into the SoC using this stuff for some products would be useful in some cases, practically a more useful EEPROM. Entirely negate the necessary for DRAM and L3/L4 cache in an SoC if its fast enough to act as L3 cache.

[Crunchy Dragon]

Just now, Agall said:

I'm going to guess it's in the metric of MB, which doesn't mean it's useless even now. Having your OS built into the SoC using this stuff for some products would be useful in some cases, practically a more useful EEPROM. Entirely negate the necessary for DRAM and L3/L4 cache in an SoC if its fast enough to act as L3 cache.

For sure.

A little SBC with this stuff onboard would be awesome to see. The price tag would obviously be less awesome, but technologically that'd be really cool.

 

I'm not saying it isn't a game-changer, but I think it'll definitely be a while before we start seeing it in traditional desktops. I'd imagine we'll probably start to see it replacing cache in traditional CPUs in the next 5-8 years, and then slowly spread from there.

[Agall]

5 minutes ago, Crunchy Dragon said:

For sure.

A little SBC with this stuff onboard would be awesome to see. The price tag would obviously be less awesome, but technologically that'd be really cool.

 

I'm not saying it isn't a game-changer, but I think it'll definitely be a while before we start seeing it in traditional desktops. I'd imagine we'll probably start to see it replacing cache in traditional CPUs in the next 5-8 years, and then slowly spread from there.

I could see it being most useful in a smartphone/watch application, where you may only need 128MB to run the machine in entirety and can eliminate most of the other storage on the device. May still need the CPU to have L1,L2 cache so it has some space to work in, or a large L3 cache. That's just my opinions based on my understanding of CPU architecture.

[Crunchy Dragon]

17 minutes ago, Agall said:

I could see it being most useful in a smartphone/watch application, where you may only need 128MB to run the machine in entirety and can eliminate most of the other storage on the device. May still need the CPU to have L1,L2 cache so it has some space to work in, or a large L3 cache. That's just my opinions based on my understanding of CPU architecture.

I think I'd see it in a smartwatch application before smartphone, since watches are closer to a straight SoC than phones(given that smartphones still need storage for things), but that door is definitely open as well. Down the road, we could see smartphones shipping with just the SoC and storage if this tech takes off the way we all think it could.

 

I agree on CPUs needing L1/L2 cache, but I think there's still some wiggle room for this to replace L3, unless I'm just being dumb.

 

Don't want to sound cliche, but this could easily be the next big thing on the computer hardware front. I'm looking forward to seeing how it plays out, what kinds of use cases it'll be viable for, and how it shakes things up.

 

Being a late adopter, I'll probably wait until it can fold out into a motorcycle before I buy it though.

[Agall]

3 minutes ago, Crunchy Dragon said:

I think I'd see it in a smartwatch application before smartphone, since watches are closer to a straight SoC than phones(given that smartphones still need storage for things), but that door is definitely open as well. Down the road, we could see smartphones shipping with just the SoC and storage if this tech takes off the way we all think it could.

 

I agree on CPUs needing L1/L2 cache, but I think there's still some wiggle room for this to replace L3, unless I'm just being dumb.

 

Don't want to sound cliche, but this could easily be the next big thing on the computer hardware front. I'm looking forward to seeing how it plays out, what kinds of use cases it'll be viable for, and how it shakes things up.

 

Being a late adopter, I'll probably wait until it can fold out into a motorcycle before I buy it though.

I'm just hoping I can full send replace my smartphone with a smartwatch, until then, I'll keep my Casio Rangeman I don't have to charge because it's used the Sun for the last 9 years I've had it. Z flip 5 solves my smartphone problems quite nicely, being most are unnecessarily big.

[leadeater]

Quote

New experimental NAND that can do literally everything

Be cheaper than NAND?

[porina]

Finally something that could be a successor to Optane?

 

>10M write cycles seems nice but it isn't practically unlimited like ram is. Trying to find some numbers for comparison, Kingston say 100k for SLC, dropping to 1k for QLC. My Optane 900p drive is warrantied for 18k cycles (10 DWPD) which feels a bit low in comparison.

 

I note in one of their slides it says no wear levelling required, so sounds like they intend to use it directly addressed and save controller overhead. I'd still be cautious about its use as a ram substitute though. Depending on what the actual minimum cycle time really is for repeat writes to the same space, I think we could be worst case looking at hours of cycle life especially in light of their "lower latency than ram" claim.

[HenrySalayne]

2 hours ago, BachChain said:

Quotes

Quote

UltraRAM is a charge-based memory that uses a floating gate, like flash NAND. Unlike flash, the charge state of the floating gate is read non-destructively by measuring the conductance of an underlying ‘channel.’ This is a major qualifier for the durability claims of 10 million write/erase cycles. Meanwhile, mainstream TLC 3D NAND might see gate degradation after a few thousand writes.

Quote

We asked the UltraRAM researchers to quantify the speeds and efficiency statements above. In terms of performance, we were told the new memory tech is expected to be capable of 0.1ns write operations, which is about 10x faster than DRAM. Last but not least, another compelling claim is of UltraRAM’s 100x lower switching energy than DRAM on the same node (1,000x lower than NAND).

I don't know what you are quoting, but there are some mistakes/inaccuracies in these quotes and Tom's Hardware tells a different story (at least now).

[wanderingfool2]

1 hour ago, leadeater said:

Be cheaper than NAND?

lol, I was thinking the same thing....no point in a technology if every bit of storage has to be hand crafted.

 

Actually, I guess it just needs to be cheaper than DRAM if their proposal is a replacement of RAM (or a new variant of the existing ones like that).

 

Then again, I'm going to assume until I see otherwise that this is just vapor ware   By the looks of things 

 

2 hours ago, BachChain said:

• Sub 0.1ns write latency
• ten million write cycle durability

Important to note the wording of the article and the claims.

 

First not sure if they corrected it or it was a mistake, but it says 1ns not 0.1 ns.

 

The next thing, they are using the words "expected".  So the tl;dr of it is a company claiming something they haven't been able to demonstrate yet in lab settings.

 

Same with the write cycle durability.  While I no doubt think it likely would be really high, they almost preface it with the fact that they haven't actually done a full test yet.

[porina]

13 minutes ago, wanderingfool2 said:

Same with the write cycle durability.  While I no doubt think it likely would be really high, they almost preface it with the fact that they haven't actually done a full test yet.

Look at the slides. The current P/E cycle life is "experiment limited", implying to me this is how far they've taken it but they haven't taken it higher yet.

[Forbidden Wafer]

Optane from Micron and Intel didn't manage to deliver its promised performance. That is all I'm going to say.

[BachChain]

1 hour ago, HenrySalayne said:

I don't know what you are quoting, but there are some mistakes/inaccuracies in these quotes and Tom's Hardware tells a different story (at least now).

Those quotes were directly from the linked article

 

https://web.archive.org/web/20230926141746/https://www.tomshardware.com/news/ultraram-demos-prototype-chip-secures-funding-to-validate-commercial-potential

[RejZoR]

While we all used to have write wear anxiety back in the early days (I was a very early adopter of SSD's with Intel X25M 80GB if anyone remembers those that I stuck in Acer Aspire One brtick of a netbook powered by first generation of Atom CPU's) and we all worried about wear and we all did tweaks so OS didn't write stuff and turned off logs and all that. Years later I had 2TB Samsung 850 Pro SSD and even though I knew it can do 1PB of writes, I kept doing compression tests on HDD out of bad habit. Now I'm finally at point where I just don't care. I have SSD's in all devices, my main system has a 4TB Firecuda 530 and I just use systems the same way we used them with HDD's when no one worried about writes.

 

For home users, it just doesn't matter as all standard NAND SSD's can survive all the write hammering. It's the data center caching that's issue and SSD's just cost too much to be used at datacenter scales because of price even today so HDD's are used for capacity and for speed, SSD caches are used. And no matter what is done there, they'll receive tons of writes regardless.

 

Would be great knowing even home drives have unlimited writes, but it's really not an issue anymore.

[wanderingfool2]

3 hours ago, porina said:

Look at the slides. The current P/E cycle life is "experiment limited", implying to me this is how far they've taken it but they haven't taken it higher yet.

The devil's in the details.

 

If lets say you looked at a singular bit of SLC NAND flash and cycle it; you will find that some samples probably also hit 10⁷...but overall during manufacturing their true numbers average/drop to 10⁶ (and for MLC sometimes even thousands).

 

Until they can come up with a method to mass produce it/produce it into actual functioning chips at some form of scale; then it is what is "expected".  It truly hasn't been tested.

 

Even their number 10⁷ that they touted, they issued a paper in IEEE regarding it, has some anomalies which the ultimate cause was unknown (but they thought they knew)

Quote

In this first-ever test, endurance is at least an order of magnitude higher than flash memory [2]. There is, however, movement of the 0/1 window throughout the process. The reason for this is currently unknown, but it is thought that it may be a result of an inconsistent channel contact that is sensitive to temperature or vibrations. Atomic force microscopy of the wet-etched channel surface shows significant etch pitting, which could cause intermittent contact with the underlying layers. An ICP etch process to create a smooth surface for consistent contact to the thin (10 nm) channel material is currently being developed in response.

Their sample was a 2x2 matrix apparently.  So I'll be more inclined to believe numbers when they actually have a more mass produced example; or one where the sample size is actually large (no 4 bits of data).

 

I mean I could be wrong, I'm not putting much effort into figuring out if it was a 2x2 matrix with 4 bits...but from what I gather from skimming it it sure seems that way.

 

The gate size also was apparently 20 μm, so if they were to reduce the gate size down further who knows if it will still maintain it's endurance.  (Just like how NAND cycles are also partially determined by the nm scale they are on)

 

https://ieeexplore.ieee.org/document/9387168

 

2 hours ago, RejZoR said:

For home users, it just doesn't matter as all standard NAND SSD's can survive all the write hammering. It's the data center caching that's issue and SSD's just cost too much to be used at datacenter scales because of price even today so HDD's are used for capacity and for speed, SSD caches are used. And no matter what is done there, they'll receive tons of writes regardless.

I disagree.  I've killed my share of SSD's in the past, and I know many others who managed to break their SSD.

 

People running their system with low ram and constantly doing things that then gets written to the SSD can be an issue; especially when you factor in the amount of users who keep their drives like 90% full or near enough full that some of the sectors get worn quicker.

[Mark Kaine]

honestly, ya'll talking about "ram" but i think this is a harddrive , because that's what they're describing,  it's just called ultraram, kinda like ramdisk... of course i could be wrong,  but it just doesn't sound like ram to me, "1 million write cycles" huhhh...

[HenrySalayne]

10 hours ago, BachChain said:

Those quotes were directly from the linked article

 

https://web.archive.org/web/20230926141746/https://www.tomshardware.com/news/ultraram-demos-prototype-chip-secures-funding-to-validate-commercial-potential

Big oof, Tom's Hardware...

 

Thanks for updating it.

[williamcll]

mmmm SRAM

 

They could market it as gamer use and people will come flooding.

[wanderingfool2]

4 hours ago, Mark Kaine said:

honestly, ya'll talking about "ram" but i think this is a harddrive , because that's what they're describing,  it's just called ultraram, kinda like ramdisk... of course i could be wrong,  but it just doesn't sound like ram to me, "1 million write cycles" huhhh...

Well I mean a harddrive is still at it's heart "RAM" (random access memory)...it's just it's persistent and slow (although at the heart of things I know it's not really what people mean when saying ram).

 

The whole issue though is that some technology really can blur the lines in terms of "what" it is; and when that happens it becomes "what do you call it".  CPU's generally use SRAM, but it's more generally called cache (because of it's ultra low latency/speed)...but crazy expensive to make compared to DRAM.  CPU has cache, which uses RAM to store less accessible stuff, then SSD, then HDD...most of it is about latency and bandwidth in regards to the category they put it in.

 

Based on what they are claiming, they are pretty much saying it's response times are better than DRAM which would make it "better" in terms of using it as RAM.  If they could prove like a 10 billion write cycle, then you could hit consumer applications like laptops (imagine sleep mode on steroids, since yo don't need to trickle charge your DRAM)...actually even if it was at like 1 mill cycles, if they have a few GB to store the OS in (and the remainder DRAM) then you get instant boots as it's already in RAM essentially.

 

This would benefit the server side of things though, specifically one where data is stored but not changing too much but needs quick access.

[LAwLz]

8 hours ago, wanderingfool2 said:

I disagree.  I've killed my share of SSD's in the past, and I know many others who managed to break their SSD.

Are you sure that was because of write cycles and not just the drive failing for other reasons? Because from what I've gathered, things like the controller in an SSD failing seems far more common than the actual NAND cells not being able to hold charge anymore. 

 

 

 

 

 

Anyway, sounds promising but I won't hold my breath for this. This might be a repeat of Optane. 

[FlyingPotato_is_taken]

What is TBRT?

Google tells me Transfer-dominated Branching Radical Telomerisation which is related to organic synthesis/chemistry.

 

Wikipedia: Triple Barrier Resonant Tunneling

The linked paper:

Quote

exploitation  of   InAs  quantum  wells  (QWs)  and  AlSb  barriers  to  create  a  triple-bar-rier  resonant-tunneling  (TBRT)  structure.  

https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202101103

DOI:  https://doi.org/10.1002/aelm.202101103

from this paper: structure and TEM image.

 

Read the paper. 

They talk a bit more about production and other challenges. Sounds to me like this technology wasn't anywhere near production ready in 2022 (same group that spun off as QuInAsQu ).

 

 

12 hours ago, porina said:

Look at the slides. The current P/E cycle life is "experiment limited", implying to me this is how far they've taken it but they haven't taken it higher yet.

The slides are from a 20 µm sized device.  The speed they claim are likely not from this but a smaller structure or theoretical. 

Also don't trust the Wikipedia article. It feels like they written it themselves.

[rcmaehl]

Probably going to be low storage capacity like Optane for more critical in-memory applications?

CPU Registers <-> L4 Cache <-> L3 Cache <-> L2 Cache <-> L1 Cache <-> "UltraRam" <-> DRAM <-> Non-Violate Storage <-> Optane <-> Regular Storage

 

Maybe?

 

 

[porina]

10 minutes ago, rcmaehl said:

Probably going to be low storage capacity like Optane for more critical in-memory applications?

There wasn't any reason for Optane not to scale other than cost, and similar may apply here. How it gets used will depend on what its benefits would cost to implement.

 

Also I'm still cautious about its use as a general ram replacement, especially if used without wear levelling as seems to be proposed. Claimed cycle life may be high compared to flash but it isn't practically unlimited like ram.