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Oracle Cranks Up The Cores To 32 With Sparc M7 Chip

oracle-sparc-m7-die-shot-370x290.jpg

 

Sweet mother of processors, this is outrageous. Keep up the good work Oracle, keep it up indeed. I guess they need this kind of absurd firepower for the kinds of stuff they run. Also, pretty processors.

 

 

With over 10 billion transistors on the die, the Sparc M7 is a whopper and will be, in terms of transistor count, the most dense processor on the market – bar none – when it ships sometime in 2015. The chip will have 32 cores, which is larger than a lot of four-socket servers had only a few years ago and which by any measure would have constituted a supercomputer two decades ago. It will be etched using Taiwan Semiconductor Manufacturing Corp’s 16 nanometer FinFET 3D transistor manufacturing node (which is sometimes also called 20 nanometer by some customers) on a 13 metal layer design.

 

 

 

The M7 will be the sixth processor that Oracle has brought to market since the Sun acquisition closed in January 2010, and it is based on the fourth generation of Sparc CMT cores (short for Chip Multi-Threading) designed by Sun and Oracle. The Sparc T3 chip for entry and midrange servers from four years ago was based on the S2 cores, the Sparc T4 and T5 chips for similar sized boxes as well as the high-end Sparc M5 servers had chips based on the S3 cores. The Sparc M6-32 system announced last year and nicknamed the Big Memory Machine was based on the Sparc M6 chip, which also used the S3 cores. Like Intel, Oracle stretches a core design over several processor generations, making a few architectural tweaks between products and changing the performance profile of each chip by changing core counts, clock speeds, cache sizes, or altering other features like system interconnects.
The S4 cores each have 16 KB of L1 instruction cache and 16 KB of L1 data cache. They are organized into clusters of four. The S4 core has a new L2 cache architecture, which allows for the same cycle count for accessing caches but allows for that cache to be 50 percent larger and still get the accesses done in the same compute time. The four cores share a 256 KB L2 instruction cache, which sits at the heart of the four-core cluster, with four independent interfaces to each core that deliver in excess of 128 GB/sec of bandwidth. (Oracle is not saying how much because it would reveal the clock speed of the processor, but Fowler did confirm that the Sparc M7 will spin faster than the current 3.6 GHz of the Sparc T5, M5, and M6 chips.) Each pair of cores shares a 256 KB L2 writeback data cache that also has interfaces to the core that provide more than 128 GB/sec of bandwidth. By having two L2 data caches, the bandwidth into the S4 core is twice as high as was the case with the S3 core. The overall L2 cache bandwidth on the four-core module is more than 1 TB/sec, which makes L2 cache bandwidth more than 8 TB/sec for the entire 32-core processor.

 

 

http://www.enterprisetech.com/2014/08/13/oracle-cranks-cores-32-sparc-m7-chip/

 

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What is a chip like this used for?

Supercomputers

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Aren't SPARC processors RISC?

"You have got to be the biggest asshole on this forum..."

-GingerbreadPK

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So.......... no minecraft then...?

 

God I'd love to have many many cores (32+) at my disposal to use.

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Supercomputers

Can I buy one? I'm assuming even if I could buy one, which I probably can't, it would be incredibly expensive.

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Can I buy one? I'm assuming even if I could buy one, which I probably can't, it would be incredibly expensive.

Welp the Tianhe-2 (currently most powerful supercomputer) uses the Xeon Phi 72 core processors I linked in the second link. It cost $390 million US. Can you afford it?

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Welp the Tianhe-2 (currently most powerful supercomputer) uses the Xeon Phi 72 core processors I linked in the second link. It cost $390 million US. Can you afford it?

We'll I meant just one CPU.

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We'll I meant just one CPU.

Ah, ok. One Xeon Phi costs $4129 US

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Two questions:

 

1. How much does this monster cost?

 

2. Can I fold on it?

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 thats a xeon phi

its a botched down x86  and very small slow  cores

 

these on the other hand are large  high clocked cores with L1 and L2 cache

 

pretty different work loads

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 thats a xeon phi

its a botched down x86  and very small slow  cores

 

these on the other hand are large  high clocked cores with L1 and L2 cache

 

pretty different work loads

16KB of L cache is not impressive. Even an i5 has more than that.

Plus the phi is used in the most powerful supercomputer, I don't think you can argue with that.

The article doesn't even list the processor's computing power.

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Two questions:

 

1. How much does this monster cost?

 

2. Can I fold on it?

 

Technically it would cost you only the cost of fabrication.

If I remember correctly, SPARC is an open source architecture.

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  • 2 weeks later...

I see Sun resurgent in this ^^

Don't ask to ask, just ask... please 🤨

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How big is the actual CPU? Compared to LGA 1150/2011 sockets?

 

Really cool nonetheless

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Supercomputers

Erm, uh...no... Sparc in supercomputers?! 0% market share in the top 1500 supercomputers. Maybe entry-level stuff, but only Oracle develops software for the Sparc platform...

Software Engineer for Suncorp (Australia), Computer Tech Enthusiast, Miami University Graduate, Nerd

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