Startup presents new architecture with virtual cores for dramatic IPC improvements

[Guest]

A Silicon Valley startup Soft Machines has raised over $125 million in funding from -among others- Samsung and AMD for further development of their VISC architecture that could bring 3x improvement in IPC ( single threaded performance).

The architecture uses virtual cores and sounds a bit like reverse hyper-threading.

Not only is Soft Machines announcing its invention to the world, but it's also demonstrating a proof a concept in action at the Linley conference: a "dual virtual core VISC" SoC prototype meant to showcase IPC improvements.

http://techreport.com/news/27259/cpu-startup-claims-to-achieve-3x-ipc-gains-with-visc-architecture

http://www.eetimes.com/document.asp?doc_id=1324364

 

A description of (another) VISC architecture from an abstract of a research paper

A variable instruction set processor provides a dictionary that enables the compiler to configure the best instruction set to use for executing the program being compiled. This paper describes Cognigine's variable instruction set communication architecture (VISC Architecture) and the implementation of a compiler that provides effective compilation and optimization support for this target. The compiler implementation involves the use of an abstract operation representation that enables the code generator to optimize toward the core architecture of the processor without committing to any specific instruction format. It then uses an enumeration approach to instruction scheduling that determines the final forms of the instructions to be generated while still adhering to the irregular constraints imposed by the architecture. The enumeration approach also allows the incorporation of dictionary reuse functionality to provide trade offs between program performance and dictionary budget.

http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=1214337

[BallGum]

Another one of those rimes where I wish I was a bit more educated about architecture to filly appreciate this. Oh well. @Lawlz or @patrickjp. Anything to add to this?

[patrickjp93]

What does VISC stand for?

I got nothing. This was outside my radar.

[The_Strict_Nein]

What does VISC stand for?

I got nothing. This was outside my radar.

Virtual Instruction Set Computing I assume, based on the fact RISC is Reduced Instruction Set Computing

[Jack.EXE]

so, they've figured out how to run a single thread on two cores?

[Shroomster]

Looks good.

[AlexGoesHigh]

What does VISC stand for?

variable instruction set communication

second quote, first line

[Guest]

so, they've figured out how to run a single thread on two cores?

looks more like they made multiple threads which change which cores they use according to the task they have

[Guest]

looks more like they made multiple threads which change which cores they use according to the task they have

A bit like AMD Kaveri's HSA, only with software not needing to be written to support it.

[Trik'Stari]

I've no idea what any of this means, but if it's better go team, if not, the bloody fools.

[Guest]

A bit like AMD Kaveri's HSA, only with software not needing to be written to support it.

Kind of, just without any graphic cores involved.

 

It will be interesting to see how long it would take Intel to adopt their upcoming architectures if this is real. Probably not in their next generation.

[dragosudeki]

Seems like one of the backers is AMD,so maybe we can see a huge bounce back in the high end AMD CPU line in the future.

[HalGameGuru]

Seems like one of the backers is AMD,so maybe we can see a huge bounce back in the high end AMD CPU line in the future.

maybe one more piece in the HSA pantheon?

[dragosudeki]

maybe one more piece in the HSA pantheon?

Yes. In fact, this seems like a key part in Heterogeneous systems. Interesting paper on VISC and HSA : http://rsim.cs.illinois.edu/Pubs/12-HotPar-VAdve.pdf

 

Note: This is for the more technically aware.

[Hazorazor]

From what I read from that post wouldnt that mean AMD may beable to create a chip which is further optimized for the task being able to swap between x86 and ARM using the virtual cores? If so I can see that being implemented in 3rd gen or so of skybridge except instead of having different x86 or ARM CPUs for the socket you can have one which does both? Correct me if I'm wrong just what I thought from reading what I could.

[Tonylu1595]

More efficient that haswell? Nice. Funny seeing apple beat everything except the softmachines.

[Ashaira]

From what I read from that post wouldnt that mean AMD may beable to create a chip which is further optimized for the task being able to swap between x86 and ARM using the virtual cores? If so I can see that being implemented in 3rd gen or so of skybridge except instead of having different x86 or ARM CPUs for the socket you can have one which does both? Correct me if I'm wrong just what I thought from reading what I could.

 

Could be. They have said that their plan is to unify arm and x86 on a single socket so that could be the next step. Can you imagine what an APU + Arm on the same chip could do with propper HSA?

[Hazorazor]

Could be. They have said that their plan is to unify arm and x86 on a single socket so that could be the next step. Can you imagine what an APU + Arm on the same chip could do with propper HSA?

Just imagining this but would be cool if the virtual cores allowed them to use many different instruction sets so that someone can make a console which plays all games from the original NES to current gen in native code. Again I'm not sure if I understood this properly.

[Techhog]

Just imagining this but would be cool if the virtual cores allowed them to use many different instruction sets so that someone can make a console which plays all games from the original NES to current gen in native code. Again I'm not sure if I understood this properly.

Do I even need to mention the legal issues with this?

[Guest]

Do I even need to mention the legal issues with this?

No because legal matters are stupid and depressing and this is a place for happy technophile dreams.

[patrickjp93]

Do I even need to mention the legal issues with this?

At least for Atari, Sega, NES, and SNES there are none remaining. 6502 is an open standard. Cell is an open standard. X86 and ARM are the only major problems.

[patrickjp93]

More efficient that haswell? Nice. Funny seeing apple beat everything except the softmachines.

How many times must we say perf/watt does not = performance. Furthermore, let's see that architecture scale up in performance, core count, and clock speed. There's still no consumer chip made by anyone more powerful than an I7 3770 except those made by Intel. In terms of workstation and exotic computing, maybe Sun and IBM do, for $10,000 a pop.

[Techhog]

At least for Atari, Sega, NES, and SNES there are none remaining. 6502 is an open standard. Cell is an open standard. X86 and ARM are the only major problems.

For one, he said all. For another thing, that ignores the very important issue of the games themselves. It would be cool for a next-gen console to have this for emulating old consoles, though.