Intel to use TSMC nodes in 15th and 16th gen

[tkitch]

 

Summary

Intel will be using tsmc 5nm in 15th generation, and then stepping down to 3nm with 16th. 

 

This could give some crazy performance in the newer chips

 

Quotes

Quote

Gelsinger also confirmed the expansion of orders to TSMC, confirming that TSMC will hold orders for Intel's Arrow and Lunar Lake CPU, GPU, and NPU chips this year, and will produce them using the N3B process, officially ushering in the Intel notebook platform that the outside world has been waiting for for many years. CPU orders.

Pat Gelsinger (Intel CEO) via ChinaTimes (Machine Translated)

 

My thoughts

 I wan planning to buy into 15th gen, but if 16th is going to 3nm? Maybe wait for it.   

 

This could be a crazy development in the cpu world 

 

Sources

 https://wccftech.com/intel-ceo-confirms-tsmc-process-nodes-next-gen-cpus-n3-arrow-lake-n3b-lunar-lake/amp/

[Shimejii]

Misleading. They are doing the GPU tile, or the GPUs theyve been doing for a few years now. They are not doing the rest of the CPU. Its not going to give crazy performance, its going to be marginal year to year.

[porina]

It'll be under the new naming system not the old gens. Next gen Arrow Lake is expected to have cores made on 20A process, and the gen after that Panther Lake on 18A process. Arrow Lake is supposed to be this year, and if it happens on time I'd expect a limited (high end only) release later on. It'll be a good indicator of how Intel have done with their process catchup plans.

[HenrySalayne]

On 2/25/2024 at 4:30 AM, Shimejii said:

Misleading. They are doing the GPU tile, or the GPUs theyve been doing for a few years now. They are not doing the rest of the CPU. Its not going to give crazy performance, its going to be marginal year to year.

The press release is talking about "CPU, NPU and GPU". I'm not sure if this is an error or if they actually plan to use TSMC for the CPU chiplets - pardon - tiles.

[porina]

1 hour ago, HenrySalayne said:

The press release is talking about "CPU, NPU and GPU". I'm not sure if this is an error or if they actually plan to use TSMC for the CPU chiplets - pardon - tiles.

https://www.digitaltrends.com/computing/intel-arrow-lake-everything-we-know/

 

https://www.hardwaretimes.com/leaked-intel-roadmap-shows-15th-gen-arrow-lake-cpus-still-based-on-20a-2nm-node-rumor/

 

Arrow Lake cores have been hinted at 20A for a while. I think Intel have said in the past that they have backup plans for 20A. It'll still be 20A, but they could make different versions of it depending on how well things go. It mainly affects manufacturing efficiency (thus cost) more than performance. Note I don't have strong feelings about either site I used above, they were the first ones I found with those slides.

 

Look at Meteor Lake for example. Cores are on Intel 4. GPU is on TSMC N5. SOC+IO on N6. Balance performance and cost, with older nodes used as appropriate.

 

I suspect 20A will be capacity constrained initially so Intel may only offer Arrow Lake on the high end to start with, and follow up the low end much later.

[leadeater]

2 hours ago, porina said:

Arrow Lake cores have been hinted at 20A for a while

Intel have consistently said CPU tiles will be manufactured on Intel fabs and I don't think they are exploring TSMC at all for that, backup plan or otherwise. Have to remember Intel is a giant fab that produces a huge amount of wafers, TSMC cannot absorb Intel's needs and every existing customer as well.

 

Figures will have changed since 2020 but Intel is only getting bigger.

[porina]

1 hour ago, leadeater said:

Figures will have changed since 2020 but Intel is only getting bigger.

Got a link to where that was from? I try to do that when I reference stuff so it can be followed up more easily.

 

In interview below, Pat claims Intel are already #2 fab worldwide counting internal consumption. They want to be #2 foundry by revenue (external customers) by 2030 only behind TSMC.

Written version link: https://morethanmoore.substack.com/p/an-interview-with-pat-gelsinger

[leadeater]

42 minutes ago, porina said:

Got a link to where that was from? I try to do that when I reference stuff so it can be followed up more easily.

Yea but the article is broken so I didn't bother, google image search got it/cached it so only place to get it. Anyway, https://www.electronicsweekly.com/news/business/capacity-leaders-wafer-size-2021-02/

 

Has the same/some info in text at least

 

42 minutes ago, porina said:

In interview below, Pat claims Intel are already #2 fab worldwide counting internal consumption

Probably only in particular node size equivalent or something like that, not in raw 300mm/200mm wafers per month. Going from 6th to 2nd is really too much in the time frame so it'll be some specific metric they are measuring against.

 

Like for example GloFo doesn't do leading edge anymore and many of the others are memory/NAND so Intel likely isn't counting them as they are also not leading edge etc etc. All about the spin heh

[RejZoR]

1 hour ago, leadeater said:

Yea but the article is broken so I didn't bother, google image search got it/cached it so only place to get it. Anyway, https://www.electronicsweekly.com/news/business/capacity-leaders-wafer-size-2021-02/

 

Has the same/some info in text at least

 

Probably only in particular node size equivalent or something like that, not in raw 300mm/200mm wafers per month. Going from 6th to 2nd is really too much in the time frame so it'll be some specific metric they are measuring against.

 

Like for example GloFo doesn't do leading edge anymore and many of the others are memory/NAND so Intel likely isn't counting them as they are also not leading edge etc etc. All about the spin heh

Industrial applications, outside of servers don't really do cutting edge. They use older much more robust and reliable nodes and they usually don't depend as much on squeezing every last drop of power out of those chips but reliability and availability. Everyone racing with 3nm nodes meanwhile they probably use something like 14nm or 7nm and they are perfectly good. Wouldn't be surprised if some still use 28nm even today for certain applications.

[porina]

9 minutes ago, RejZoR said:

Wouldn't be surprised if some still use 28nm even today for certain applications.

You use the right nodes appropriate for the product. I think some of my Canon big camera sensors were made on 180nm. For that specific use case, you don't get much benefit moving to newer nodes.

 

Here's a visualisation of TSMC's revenue by node. 5+3 make roughly half of their revenue. Older nodes make much less per wafer, so if you count by volume leading edge is only a small part. There is demand for both leading edge and mature nodes. Even Intel is making new 12nm offerings in partnership with UMC as part of their foundry service. It'll be a kind of general node for those that don't need to be near leading edge.

 

[leadeater]

4 hours ago, RejZoR said:

Industrial applications, outside of servers don't really do cutting edge. They use older much more robust and reliable nodes and they usually don't depend as much on squeezing every last drop of power out of those chips but reliability and availability. Everyone racing with 3nm nodes meanwhile they probably use something like 14nm or 7nm and they are perfectly good. Wouldn't be surprised if some still use 28nm even today for certain applications.

Even 90nm is still used. Even Intel has Fabs that do 90nm and larger too if the public info is still up to date and correct.

 

Anything power related, MOSFETs etc, go all the way up to like 800nm.

[Kisai]

14 hours ago, RejZoR said:

 Wouldn't be surprised if some still use 28nm even today for certain applications.

The smaller the node, the less reliable and less durable it becomes, which is why NAND flash kinda is stuck at 16nm for SLC. https://web.archive.org/web/20210517040328/https://www.skhynix.com/eng/about/history2010.jsp

 

No SLC has been developed since. Now we're at:

https://asia.nikkei.com/Business/Tech/Semiconductors/SK-Hynix-working-on-cutting-edge-321-layer-NAND-flash-memory#:~:text=SK Hynix is the first,the first half of 2025.

 

https://mdpi-res.com/d_attachment/electronics/electronics-10-03156/article_deploy/electronics-10-03156-v2.pdf?version=1640157777#:~:text=In the CMOS under Array,is available for CMOS circuits.

Quote

After 2D NAND reached the scaling limit around 15 nm in process node, 3D NAND was proposed as a solution for the continuous NAND scaling [1]. The 3D NAND was introduced into production with 24 layers and MLC technology [2]. The scaling trend of the areal density of 2D NAND and 3D NAND is summarized based on the NAND publications in IEEE ISSCC conferences, (Figure 1). As seen in Figure 1, 3D NAND successfully replaced 2D NAND and has achieved more than 10 Gb/mm2 areal density [2–31].

Only things that really matter what the process node is are logic circuits for math. Once you're off to storage, network or i/o, the process node doesn't really need to "get faster", it needs to "become more reliable". For example, we've had 10/100 Ethernet since the 90's, and have had Gbit on PowerMac's since 2000. So we've gone 24 years without any innovation in Gbit ethernet, and what has brought Gbit into standard on desktop PC's was Realtek's PCIe Gbit chips... in 2005, which was probably 90nm. A lot of the stuff on the cheapy RTL chips was software, so that built in ethernet was passible, but not enterprise grade. Gbit Ethernet has not gotten any faster, because it can't. What do you get by shrinking the process node? less energy use? Does that make the chip any cheaper?

 

2.5Gbit? 10gbit? It is appearing in consumer products. Just only Apple seems it necessary to put it into it's hardware, and not ALL of it's hardware. 

 

Then you have SATA and USB, and really, how much faster do you need the i/o die to be? the interconnect between the i/o die (or traditionally the south bridge) hasn't changed and on AMD it's still just a PCIe interconnect.

 

Most gains with the i/o die are physical space and energy use, but we aren't seeing any new functionality being added to justify it. I'd rather have more PCIe lanes so I can have several PCIe NVMe drives AND a GPU. But Intel and AMD are like "nah, you only need 20 lanes, or you need our server product."

 

[StDragon]

46 minutes ago, Kisai said:

2.5Gbit? 10gbit? It is appearing in consumer products.

An X550-T2 NIC was released in Q1 2016 with an MSRP of $294. As of today, it can be found for around $200 (give or take).

Finding a cheap Base-T 10gig NIC starts around $70. So instead we have the stupid 2.5Gb standard and not all 10gig switches support it.

 

Price high because of fabrication supply?? I'm calling shenanigans of market collusion and manipulation.

[leadeater]

2 hours ago, StDragon said:

An X550-T2 NIC was released in Q1 2016 with an MSRP of $294. As of today, it can be found for around $200 (give or take).

Finding a cheap Base-T 10gig NIC starts around $70. So instead we have the stupid 2.5Gb standard and not all 10gig switches support it.

 

Price high because of fabrication supply?? I'm calling shenanigans of market collusion and manipulation.

The problem wasn't the NICs, it was the switch chips and processors in network equipment, having lots of 10Gb ports requires supporting hardware capability for it and that was expensive.

 

2.5Gb/5Gb should have come 5-10 years sooner so it had a real point, now it's stupid because we actually can do 10Gb cheaply (end to end) but all that effort went in to creating "Multigigabit Ethernet" standard and nobody wants to lose money on it.

[porina]

3 hours ago, Kisai said:

The smaller the node, the less reliable and less durable it becomes, which is why NAND flash kinda is stuck at 16nm for SLC. 

 

No SLC has been developed since.

I'm not sure it is a technical reason but an economic one. There just isn't a point to manufacture pure SLC when you can run higher density flash in pseudo-SLC mode and get the same performance and similar endurance.

 

3 hours ago, Kisai said:

Gbit Ethernet has not gotten any faster, because it can't.

Something defined at a speed remains at that speed! Didn't see that coming.

 

3 hours ago, Kisai said:

Most gains with the i/o die are physical space and energy use, but we aren't seeing any new functionality being added to justify it. I'd rather have more PCIe lanes so I can have several PCIe NVMe drives AND a GPU. But Intel and AMD are like "nah, you only need 20 lanes, or you need our server product."

Zen 4 IOD does have the iGPU now, not present in older ones. On lanes, you're looking at it from a very enthusiast perspective. For the vast majority of the marketplace they're actually targeting the lane count is more than sufficient.

 

There is a disjoin I see in today's PC space in that we lost affordable HEDT thanks to AMDs more cores approach. HEDT used to start at the higher end of consumer tier offerings and gave those platform benefits, which were far more valuable to me than more cores.

 

2 minutes ago, leadeater said:

2.5Gb/5Gb should have come 5-10 years sooner so it had a real point, now it's stupid because we actually can do 10Gb cheaply (end to end) but all that effort went in to creating "Multigigabit Ethernet" standard and nobody wants to lose money on it.

I went 2.5GbE for my home usage in 2020 since, at the time, 10GbE was still far more expensive unless you went the route of used enterprise gear using SFP. In a quick look, that still seems to apply today.

 

UK Amazon pricing:

2.5GbE switches, starting around £60 for at least 4 ports plus uplink, and most PCIe adapters are around £22 with a single outlier at £10.

10GbE switches, starting around £300 for 4 copper ports plus uplink, and most PCIe adapters are around £90 with single cheapest at £59.

 

10GbE copper, buying new in UK, is going to work out much more expensive than 2.5GbE. If you really need the speed, you pay for it. 2.5GbE gives a nice uplift over 1GbE and the cost is getting marginal.

 

For my personal use case, 2.5GbE is the sweet spot since it aligns closely with the peak transfer rate of a single hard disk in my NAS. 

[leadeater]

3 minutes ago, porina said:

10GbE copper, buying new in UK, is going to work out much more expensive than 2.5GbE. If you really need the speed, you pay for it. 2.5GbE gives a nice uplift over 1GbE and the cost is getting marginal.

2.5Gb is great to have of course, but the reason 10Gb hasn't gotten cheaper is because of the massive investment in multigigabit. Price drops with volume and since we're making much more multigigabit ICs (controllers/switch chips) that go on motherboards, NIC and switches etc it'll always be cheaper than the older 10Gb standard.

 

It is better to have it, but the 10 years between 2006 (10Gb) and 2016 (2.5/5 Gb) we should have developed it sooner. I would argue it should have been in 2006 and been 2.5/5/10 Gb from the get go and then give the choice of which actual speeds are allowed on a per product basis determined by the device manufacture. That way you don't need a network switch that can handle 8x 10Gb ports when you only offer it at 8x 2.5Gb actual.