New Xeon platform leaks, named Skylake Purley, coming in 2017.

[Bouzoo]

Yep, it's WCCFTech. But hey, better than anything. So what is this? It's only about Xeons (as stated in the title), so average consumers, don't hold your breath. Well it's supposed to be "the biggest update since Nehalem". Quite a claim hey? But what is it really?

 

Along with the improved performance per watt that comes with every article iteration, Skylake EX Purley will actually ship with 6 Channels of DDR4 as opposed to 4. It will also include the AVX 512 instruction set and will boast the 100G OmniPath interconnect. Skylake Purley will also have Cannonlake graphics support not to mention FPGA integration (another important upgrade). The FPGA will be able to execute programmable logic as opposed to the Skylake processor.

More RAM, and a iGPU? Sounds quite good. And it's coming in 2017.

 

 

So Skylake Server CPU, New PCH and few other controllers. Well that was expected- I know Xeon Phi are gonna use Omni-Path so is this gonna be 2nd gen (I think)? Now that's gonna be interesting.

 

Now let's go to the details (this is mostly c/p, but it will explain it far better than I could)

One of the biggest advancements that Skylake will have is the Intel Omnipath Architecture integration which will be called Storm Lake (Generation 1). The PCH will be codenamed Lewisburg while as it will also ship with updated Ethernet controllers. Another very important point to note is that the platform will be scalable up to 8 Sockets – which is frankly an absolutely insane amount for CPUs working in tandem in any given configuration. Specific SKUs have not been disclosed at this time. Skylake EX Purley will be spread out amongst the entire scalable segment – unlike the previous iterations. The TDP will be configurable from 45W to 165W and will require Socket P. Another interesting point to note is the fact that not only will Purley update the number of PCIe slots to 48 but they will finally be configurable in x4, x8 and x16 divisions ( a major update).

Broadwell will be split into two categories depending on the target market (and the scalability required). There is the Brickland platform for the Broadwell side of things on the high end scalable segment. The SKU families E7 8800/4800 V3 and E7 8800/4800 V4 are specified in a succeeding order. The 4S segment also contains the Grantley- EP 4S platform which once again has two iterations, one planned for 2015 and the other for 2016. The SKU family 4600 v3 and 4600 V4 has been specified. At the 2S segment of the market is the Grantley Platform. The SKU family reported here is the Xeon E5 2600v4. Brickland with Bridewell-EX CPU will have 115 to 165W TDP and will utilize the Socket R1. The usual 4 Channels of DDR4 will compliment the setup and 32 lanes of PCIe (per CPU). Grantley with Braodwell-EP will have configurable TDP of 55-145W and a separate 165W setup. Their will be the usual 4 Channels of DDR4 memory and 40 lanes of PCIe.

 

 

 

 

 

Now what do we get? Option for more RAM, new socket (Socket P), iGPU, new PCH which sounds really interesting, some nice TDP and Omni-Path Arcihitecture (+some few more things). It all looks very promising, so to people more experienced with Xeons and server gear, what do you think?

OT: Every time I read the name, I think about Cats.  :blink:

 

Yours truly. WCCFTech.

[Nexxus]

I thought this was a fluid leak reading the title. I was very alarmed. 

[Flight1sim]

Wow i love your post, a TON of information! Good job

Also, wow dis could be gud

[Embattled]

Can't. Hold. All. These. Intel. Roadmap. Leaks.

[tsk]

I was almost certain it would be PCIe 4.0

[Delusional Phil]

28 cores wiht HT = 56 threads .... Can't handle that much performance and that pricetag ... 

[-TesseracT-]

I was almost certain it would be PCIe 4.0

Do we need it?

[TroubleKlef]

Xeon CPUs share sockets with X-(xx) right?

[LukaP]

Xeon CPUs share sockets with X-(xx) right?

Yes, but they dont always work without a C series chipset.

[tsk]

Do we need it?

Going into 2018 I'll be willing to bet yes.

[LukaP]

Going into 2018 I'll be willing to bet yes.

I wouldnt. With most HPC moving to on board solutions (socketed Xeon + Xeon Phi, Pascal being a simple socket using NVLink) id say PCIe is a dying tech in that market. In consumer space it would be interesting mainly because GPUs could then run off of PCIe x8 and leave more lanes for storage.

[Guest Strangerbob]

Am i the only one whos bored out of his mind with anything intel related... for the past 5 years?

[LukaP]

Am i the only one whos bored out of his mind with anything intel related... for the past 5 years?

This is actually exciting. we get new instructions and a lot of cores, DMI3, new version of QPI (i assume UPI stands for Universal path interconnect, so perhaps more to come from this), more PCIe lanes, more RAM channels, as well as a new process node and architecture.

 

This is about 439473x more interesting than Haswell EX was

[tsk]

I wouldnt. With most HPC moving to on board solutions (socketed Xeon + Xeon Phi, Pascal being a simple socket using NVLink) id say PCIe is a dying tech in that market. In consumer space it would be interesting mainly because GPUs could then run off of PCIe x8 and leave more lanes for storage.

Indeed, I was thinking of storage using x4 lanes.

[LukaP]

Indeed, I was thinking of storage using x4 lanes.

Then its more of a problem of giving it more lanes, rather than faster ones. Current 3.0 x4 SSDs dont even get close to the bandwith it can support, and we already see that it is not really a bottleneck for power users. 

 

The only time it is is when you have your mass storage over SATA HDDs. And with more PCIe3 and SSDs getting cheaper, you will be able to move more of that to PCIe based SSDs. For that there is 48 lanes on Skylake, instead of 40 on Haswell.

[patrickjp93]

Do we need it?

HPC space does. PCIe 3.0 is a big bottleneck in GPGPU computing for LARGE data sets.

[LukaP]

HPC space does. PCIe 3.0 is a big bottleneck in GPGPU computing for LARGE data sets.

NV link, as well as other new technologies will replace PCIe in the coming years. (for ultra fast communications) PCIe gets exponentially more expensive to control with each version

 

UPI might be one of those...

[Trik'Stari]

NV link, as well as other new technologies will replace PCIe in the coming years. (for ultra fast communications) PCIe gets exponentially more expensive to control with each version

 

UPI might be one of those...

But will it run MC on amplified world type, without chunk load lag?

[LukaP]

But will it run MC on amplified world type, without chunk load lag?

nothing short of a real brain on steroids can do that.

[Trik'Stari]

nothing short of a real brain on steroids can do that.

damn.....

[KirbyTech]

I was expecting PCIE 4.0 and more pcie lanes as so many things now are ad ins. With nvme storage and m.2 pcie drives taking up lanes it seems for workstations and servers that pcie lanes are starting to become an issue in more cases.

[Bouzoo]

NV link, as well as other new technologies will replace PCIe in the coming years. (for ultra fast communications) PCIe gets exponentially more expensive to control with each version

 

UPI might be one of those...

Since I'm not into those new technologies, NVlink is only for Nvidia right? Yeah, dumb question. If it is, what's the alternative for AMD?

[patrickjp93]

NV link, as well as other new technologies will replace PCIe in the coming years. (for ultra fast communications) PCIe gets exponentially more expensive to control with each version

 

UPI might be one of those...

Neither AMD nor Intel will buy into NVLink, though I do agree new connectors will be needed soon based on cost. Though in the meantime, PCIe 4 is desperately needed for exascale computing until alternate solutions are devised and made popular.

[patrickjp93]

I was expecting PCIE 4.0 and more pcie lanes as so many things now are ad ins. With nvme storage and m.2 pcie drives taking up lanes it seems for workstations and servers that pcie lanes are starting to become an issue in more cases.

The chipsets are already coming with more PCIe lanes for the storage options.

[LukaP]

Since I'm not into those new technologies, NVlink is only for Nvidia right? Yeah, dumb question. If it is, what's the alternative for AMD?

They arent a part of HPC market anyway.

 

Neither AMD nor Intel will buy into NVLink, though I do agree new connectors will be needed soon based on cost. Though in the meantime, PCIe 4 is desperately needed for exascale computing until alternate solutions are devised and made popular.

wasnt it leaked some time ago that Skylake or Cannonlake EX will support NVLink optionally?