Glo-Fo Declares 12nm FDSOI For 2019

[patrickjp93]

http://www.globalfoundries.com/newsroom/press-releases/2016/09/07/globalfoundries-extends-fdx-roadmap-with-12nm-fd-soi-technology

 

Sorry, on phone and can't use quotes. Will edit when I can.

Spoiler

GLOBALFOUNDRIES today unveiled a new 12nm FD-SOI semiconductor technology, extending its leadership position by offering the industry’s first multi-node FD-SOI roadmap. Building on the success of its 22FDX offering, the company’s next-generation 12FDX platform is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles.

 

12FDX sets a new standard for system integration, providing an optimized platform for combining radio frequency (RF), analog, embedded memory, and advanced logic onto a single chip. The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency.

 

“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”

 

GLOBALFOUNDRIES’ new 12FDX technology is built on a 12nm fully-depleted silicon-on-insulator (FD-SOI) platform, enabling the performance of 10nm FinFET with better power consumption and lower cost than 16nm FinFET. The platform offers a full node of scaling benefit, delivering a 15 percent performance boost over today’s FinFET technologies and as much as 50 percent lower power consumption.

It seems the goal of this node is to be a jack-of trades node that isn't as costly as FinFET design (though the cost of FDSOI substrate wafers is far higher than standard bulk silicon, so there's probably some creative booking to be able to say this).

 

I thought IBM's Power 9 would be based on a 14nm FDSOI design, but with the chips due in another year, I'm now wondering if IBM will use GloFo's 14nm LPP or HP process instead or just stick with 22nm FDSOI. Interesting times we live in...

[Agosto]

Maybe Zen++ on 12nm FDSOI?

[VerticalDiscussions]

Oh thats quite cool! This could be something really useful for smartphones power efficiency and performance improvement issues, which would open a possibility for multi-cpu configurations, like Turing "claims" to be on the making. If a 10nm ARM cpu was made using FDSOI, it would be like a 7/8nm FinFet process used by Samsung/Apple for example?

[Vode]

So basically this is a more legit 12nm process as opposed to the "14nm" and "16nm" FinFet that actually closer to 20nm.

[Coaxialgamer]

48 minutes ago, Vode said:

So basically this is a more legit 12nm process as opposed to the "14nm" and "16nm" FinFet that actually closer to 20nm.

Gloflo 14nm has a standardized node value of 16.6nm, so it's closer to 14nm. Tsmc 16nm is 18.8nm though 

[Coaxialgamer]

I'm actually counting on fd soi to make progress.  Similar performance to finfet,  but can be significantly cheaper in some cases. 

[rattacko123]

Soo, whats the different between finfet and fd soi? 

20 minutes ago, Coaxialgamer said:

I'm actually counting on fd soi to make progress.  Similar performance to finfet,  but can be significantly cheaper in some cases. 

cost of chip manufacturing isn't a major factor (profit margins are really high), its more of the R&D that's expensive

[patrickjp93]

1 hour ago, Vode said:

So basically this is a more legit 12nm process as opposed to the "14nm" and "16nm" FinFet that actually closer to 20nm.

 

39 minutes ago, Coaxialgamer said:

Gloflo 14nm has a standardized node value of 16.6nm, so it's closer to 14nm. Tsmc 16nm is 18.8nm though 

You have the measurements source for that?

 

It's an IBM-designed node that, from what I am guessing, uses 14nm BEOL and 10nm features.

 

17 minutes ago, rattacko123 said:

Soo, whats the different between finfet and fd soi? 

cost of chip manufacturing isn't a major factor (profit margins are really high), its more of the R&D that's expensive

FDSOI is a planar process. Design costs (which are very large btw) are much lower on planar processes. It also has far better power qualities than FinFET, but it tends to give up clock speed to do it. Many foundries will combine the two techniques in the future to get everything they can out of a new node.

[Coaxialgamer]

26 minutes ago, rattacko123 said:

Soo, whats the different between finfet and fd soi? 

cost of chip manufacturing isn't a major factor (profit margins are really high), its more of the R&D that's expensive

actually it is . Per transistor cost is actually going up because of the heavy amount of lithography used to make finfet's . Fd soi is Planar and much simpler to build

[DocSwag]

24 minutes ago, patrickjp93 said:

 

You have the measurements source for that?

 

It's an IBM-designed node that, from what I am guessing, uses 14nm BEOL and 10nm features.

 

FDSOI is a planar process. Design costs (which are very large btw) are much lower on planar processes. It also has far better power qualities than FinFET, but it tends to give up clock speed to do it. Many foundries will combine the two techniques in the future to get everything they can out of a new node.

So basically FDSOI is a process technology better suited for mobile parts and FinFET is better suited for high performance parts (hen compared to each other)?

[Coaxialgamer]

10 minutes ago, patrickjp93 said:

 

You have the measurements source for that?

 

It's an IBM-designed node that, from what I am guessing, uses 14nm BEOL and 10nm features.

I used to , however i cannot find it at the moment . there is a formula to calculate this value using a few values including half pitches . According to that , intel had a node value of 13.4nm ( 14nm ) , gloflo/samsung had a value of 16.6nm ( 14nm ) and tsmc had a value of 18.8nm ( 16nm)

[Vode]

2 minutes ago, DocSwag said:

So basically FDSOI is a process technology better suited for mobile parts and FinFET is better suited for high performance parts (hen compared to each other)?

Not sure if FDSOI is actually better for lower power apps than FinFet. I think it's more cost effective.

 

But FinFet is better suited for high power chips. AMD and Nvidia both skipped the planar 20nm node because it would have worked out due to yield on the big chips or performance characteristics of the node.

[patrickjp93]

25 minutes ago, DocSwag said:

So basically FDSOI is a process technology better suited for mobile parts and FinFET is better suited for high performance parts (hen compared to each other)?

Counting Power 8 and Sparc 7 as exceptions, yes.

 

20 minutes ago, Vode said:

Not sure if FDSOI is actually better for lower power apps than FinFet. I think it's more cost effective.

 

But FinFet is better suited for high power chips. AMD and Nvidia both skipped the planar 20nm node because it would have worked out due to yield on the big chips or performance characteristics of the node.

It is. Most of the major microcontrollers have been made on 22nm FDSOI for that reason.

 

The 20nm snafu was much more because of TSMC's folly in not choosing FinFET or FDSOI when Intel and IBM had already made the jump. Samsung at least knew not to make guarantees it could get a 20nm HP process working.

[Prysin]

16 hours ago, patrickjp93 said:

http://www.globalfoundries.com/newsroom/press-releases/2016/09/07/globalfoundries-extends-fdx-roadmap-with-12nm-fd-soi-technology

 

Sorry, on phone and can't use quotes. Will edit when I can.

  Reveal hidden contents

GLOBALFOUNDRIES today unveiled a new 12nm FD-SOI semiconductor technology, extending its leadership position by offering the industry’s first multi-node FD-SOI roadmap. Building on the success of its 22FDX offering, the company’s next-generation 12FDX platform is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles.

 

12FDX sets a new standard for system integration, providing an optimized platform for combining radio frequency (RF), analog, embedded memory, and advanced logic onto a single chip. The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency.

 

“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”

 

GLOBALFOUNDRIES’ new 12FDX technology is built on a 12nm fully-depleted silicon-on-insulator (FD-SOI) platform, enabling the performance of 10nm FinFET with better power consumption and lower cost than 16nm FinFET. The platform offers a full node of scaling benefit, delivering a 15 percent performance boost over today’s FinFET technologies and as much as 50 percent lower power consumption.

It seems the goal of this node is to be a jack-of trades node that isn't as costly as FinFET design (though the cost of FDSOI substrate wafers is far higher than standard bulk silicon, so there's probably some creative booking to be able to say this).

 

I thought IBM's Power 9 would be based on a 14nm FDSOI design, but with the chips due in another year, I'm now wondering if IBM will use GloFo's 14nm LPP or HP process instead or just stick with 22nm FDSOI. Interesting times we live in...

y u no skype?

Also, Power 9, wasnt that supposed to release Q1 or Q2 17?
Given that i havent heard any indication that IBM is looking to be too agressive on reducing power draw compared to Power 8, i guess 14nm HP is more likely if they are going to change node at all.

[Vode]

 

3 hours ago, patrickjp93 said:

 

 

It is. Most of the major microcontrollers have been made on 22nm FDSOI for that reason.

 

The 20nm snafu was much more because of TSMC's folly in not choosing FinFET or FDSOI when Intel and IBM had already made the jump. Samsung at least knew not to make guarantees it could get a 20nm HP process working.

Oh ok. Thanks for the info!

[Citadelen]

5 hours ago, rattacko123 said:

Soo, whats the different between finfet and fd soi? 

cost of chip manufacturing isn't a major factor (profit margins are really high), its more of the R&D that's expensive

EUV says hi.

[BuckGup]

gud

[patrickjp93]

2 hours ago, Citadelen said:

EUV says hi.

Both process rules require it below 10nm.

[Citadelen]

17 hours ago, patrickjp93 said:

Both process rules require it below 10nm.

I know, I was picking them up on saying that manufacturing isn't expensive.

[Prysin]

On 12/09/2016 at 4:10 PM, Citadelen said:

I know, I was picking them up on saying that manufacturing isn't expensive.

EUV manufacturing is not expensive. Once manufacturing starts. But atm it is in RnD phase, which is MUCH more expensive.

[Coaxialgamer]

On 9/11/2016 at 2:59 PM, patrickjp93 said:

You have the measurements source for that?

 

It's an IBM-designed node that, from what I am guessing, uses 14nm BEOL and 10nm features.

I just stumbled upon it today while looking around . 

formula is 

Standard Node = 0.14 x (CPHP x MMHP)^0.67

Where CPHP is the contacted polysilicon half-pitch and MMHP is the minimum metal half pitch.

 

from : https://www.semiwiki.com/forum/content/6160-2016-leading-edge-semiconductor-landscape.html

[patrickjp93]

On September 15, 2559 BE at 1:47 AM, Prysin said:

EUV manufacturing is not expensive. Once manufacturing starts. But atm it is in RnD phase, which is MUCH more expensive.

Eh, it's still expensive because of the mask complexity and having to replace light sources significantly more often.