Mainstream DDR5 Memory Modules Pictured, Rolling Out For Mass Production & Coming To Intel & AMD’s Next-Gen Platforms Soon!

[PeachGr]

12 minutes ago, Ydfhlx said:

Remember that latency measured in miliseconds is CL/speed, so a DDR5 CL40 4800 is comparable to DDR4 2933 CL24 - so for a "stock" module it's comparable.

Well when an architecture of mobo and CPU changes, you can't really judge the new RAM by today's standards. Ddr3 had lower cl but it's slower and incomparable.

Also not all Rams ate the same. There are 2200mhz and 5000mhz on ddr4 and also cl22 and cl14, but I think that cl will be a higher number, not that it will mean anything, because in the end, we will have better results in the system

[TheCoder2019]

12 minutes ago, PeachGr said:

Well when an architecture of mobo and CPU changes, you can't really judge the new RAM by today's standards. Ddr3 had lower cl but it's slower and incomparable.

Also not all Rams ate the same. There are 2200mhz and 5000mhz on ddr4 and also cl22 and cl14, but I think that cl will be a higher number, not that it will mean anything, because in the end, we will have better results in the system

With the higher RAM speeds, will new CPUs have to be released to utilize the extra speed?

[porina]

7 hours ago, leadeater said:

With the Zen 2 IF and memory improvement that means the read bandwidth is 50GB/s and write 25GB/s, I think that other source did 50x2 

Took a while but seems we agreed then?  

 

6 hours ago, PianoPlayer88Key said:

My big concern with DDR5 isn't so much getting much faster memory (although that would be nice too); but I really need much higher capacities.

The on die ECC is a nod in that direction. The chance of a bad ram bit goes up with capacity, so ECC will mitigate against that.

 

6 hours ago, PianoPlayer88Key said:

For me, 512GB RAM would be a bare minimum, and I'd really like 1 or 2 TB RAM (more if I get registered ECC which I want support for, or 8 or more DIMM slots).

Good luck with that. If you want the lower cost of a consumer level system it seems unlikely you'll get beyond 128GB (4x32GB), maybe 256GB if DDR5 steps up to 64GB modules. I don't see them going above 4 slots still. You'll probably have to look at HEDT level for 8 slots.

 

6 hours ago, PianoPlayer88Key said:

Also ECC will be an absolute requirement for me.  I'm glad DDR5 at least supports some sort of ECC, although comments about chip vs module level ECC make me concerned about some platforms still not properly supporting it (like consumer Intel chipsets like my laptop's Z170 or desktop's Z97 don't support ECC on DDR4/3).

Chip level ECC is baked into the modules. If the system supports DDR5, it will support the die level ECC. Note right now, no consumer platform supports ECC. No, Zen 2 doesn't. It has functionality for it, but it is still unsupported. If you really care about ECC, that's not good enough. On Intel side, some consumer level CPUs actually support ECC, but they require server chipset to use it, so strictly speaking they're not consumer platform at that point.

 

6 hours ago, PianoPlayer88Key said:

Also support for registered ECC would be really nice so I can have even higher capacities.  Any ideas of NON-MARKETING/SEGMENTING reasons why consumer platforms don't support registered ECC?

 

I've sometimes wondered why we don't see 3 or 4 DIMMs per channel, for higher capacities, at least on consumer platform.

Same reason as always: cost. It doesn't come for free. There is more design work in the platform. There is more validation. For use cases that will never need it, there's no point adding that cost and complexity in for the one person asking for it. The solution in those cases is to look at HEDT/workstation/server as appropriate.

 

Quote

Another thing ... any ideas why memory latency has generally gotten looser over the past several generations?

It hasn't. The cycle count goes up only because the speeds go up. If you look at like for like modules the real time latency remains relatively constant. That's probably more a "laws of physics" thing. By like for like, compare standard modules with standard modules, enthusiast modules with enthusiast modules. There's a fair gap between them.

 

[Albal_156]

Is this going to be a problem in the sense of DDR speeds being more than the speed of our CPUs. I wonder.

[TheCoder2019]

26 minutes ago, Albal_156 said:

Is this going to be a problem in the sense of DDR speeds being more than the speed of our CPUs. I wonder.

My CPU is clocked at 3.6GHz right now, so 10GHz RAM may not be the best thing... See below, or above

 

[PeachGr]

3 hours ago, TheCoder2019 said:

With the higher RAM speeds, will new CPUs have to be released to utilize the extra speed?

well ram speed is "up-to"
That reminds me the first gen ryzen that couldnt run RAM as fast as the maximum of the written specs
Even intel's 10th can't run extrem ram speeds as 11th gen
But again, maybe they' ll find a way to use it, it's new architechture as i said.
Also i guess we ll have to wait for the 2nd or 3rd generation to gain full benefits

[porina]

12 hours ago, Albal_156 said:

Is this going to be a problem in the sense of DDR speeds being more than the speed of our CPUs. I wonder.

Irrelevant. They're operating separately. Ram quite simply is not fast enough compared to the core potential of most current systems and in many (but not all) cases impacts performance, so any improvement will help. It does kinda assume good data flow within the CPU and I think AMD may have to do more work than Intel in that department due to their design choices. Intel generally has been async but AMD tries to tie to IF so that adds a layer of complexity.

 

Roughly speaking, (assuming two modules on a consumer platform) with DDR5 then quad core CPUs will finally be practically unlimited by ram bandwidth. 6 cores might be getting close to that point but 8+ cores can always use more. This only considers core usage, and not iGPU considerations which can probably use even more.

[leadeater]

25 minutes ago, porina said:

Irrelevant. They're operating separately. Ram quite simply is not fast enough compared to the core potential of most current systems and in many (but not all) cases impacts performance, so any improvement will help. It does kinda assume good data flow within the CPU and I think AMD may have to do more work than Intel in that department due to their design choices. Intel generally has been async but AMD tries to tie to IF so that adds a layer of complexity.

 

Roughly speaking, (assuming two modules on a consumer platform) with DDR5 then quad core CPUs will finally be practically unlimited by ram bandwidth. 6 cores might be getting close to that point but 8+ cores can always use more. This only considers core usage, and not iGPU considerations which can probably use even more.

If/when they shrink the IOD to 7nm then they might double the GMI interfaces to each CCD, would also require an updated CCD so maybe only when those move to 5nm or 7nm refresh of them isn't out of the question either.

 

That's the nice part about their archecture and design, you can scale out things like the GMI interfaces but that comes at the cost of die area and package complexity.

 

The GloFlo contract is almost up soon so we'll see how that shakes up the IOD.

[porina]

1 hour ago, leadeater said:

If/when they shrink the IOD to 7nm then they might double the GMI interfaces to each CCD, would also require an updated CCD so maybe only when those move to 5nm or 7nm refresh of them isn't out of the question either.

It might be an interesting thought exercise, what could they do? There's two obvious questions, with not so obvious answers. I might have a deeper think about this later.

 

1, Faster ram implies either they also run faster IF clock if they want to stay synchronous, or have to do some kind of conversion (async).

2, Increase ram bandwidth would imply more IF bandwidth, however it is delivered. Makes more sense for 2+ CCD systems?

[Albal_156]

10 hours ago, porina said:

It might be an interesting thought exercise, what could they do? There's two obvious questions, with not so obvious answers. I might have a deeper think about this later.

 

1, Faster ram implies either they also run faster IF clock if they want to stay synchronous, or have to do some kind of conversion (async).

2, Increase ram bandwidth would imply more IF bandwidth, however it is delivered. Makes more sense for 2+ CCD systems?

So AMD might increase core counts again sometime in the future after the I/OD is updated to 7nm and once they are on DDR5? Theres also Raphael coming in Zen 4 with RDNA2+ graphics. I think Zen4 is when we will finally see the low end budget dGPU market be over (it kind of already is as AMD hasn't offered a stellar alternative ot the RX 580 yet). CPUs will have such great iGPUs and DDR5 will have such great bandwidth and speed that 1080p High will probably be possible in the latest titles maybe even 1440p depending on what model of GPU AMD implements in Zen 4.

[porina]

6 minutes ago, Albal_156 said:

I think Zen4 is when we will finally see the low end budget dGPU market be over (it kind of already is as AMD hasn't offered a stellar alternative ot the RX 580 yet). CPUs will have such great iGPUs and DDR5 will have such great bandwidth and speed that 1080p High will probably be possible in the latest titles maybe even 1440p depending on what model of GPU AMD implements in Zen 4.

If you consider low end graphics to be RX 580 level, then I don't think consumer DDR5 APUs will come anywhere near that. However, IMO low end gaming graphics would be GTX 1050 level, and I think DDR5 era APUs could be competitive against that.

 

This all comes down to bandwidth. DDR5 is faster than DDR4, but still falls way behind GPU levels. Let's say at best you get two module DDR5-6400 paired with a future APU, ass you're not going for very high speed grades typically with an APU part. That'll get you around 100GB/s bandwidth, comparable to the 1050, but you'd need to more than double it to reach the RX 580. Maybe if they include big enough infinity cache in the APUs that might help, but I doubt they will do so as they take a huge proportion of silicon on RDNA2.

[StDragon]

On 4/26/2021 at 2:37 PM, porina said:

Chip level ECC is baked into the modules. If the system supports DDR5, it will support the die level ECC. Note right now, no consumer platform supports ECC. No, Zen 2 doesn't. It has functionality for it, but it is still unsupported. If you really care about ECC, that's not good enough. On Intel side, some consumer level CPUs actually support ECC, but they require server chipset to use it, so strictly speaking they're not consumer platform at that point

Zen 2 does support ECC with select X570 boards from Gigabyte and ASRock (such as the X570 Taichi)

FYI, I have an old Phenom II system running ECC as well; all sorts of scrubbing options. Tested and verified with Memtest86.

As for DDR5, that's ECC within the DIMM, but the MB and CPU has to support ECC from the DIMM to the CPU I/O controller. Additionally, DDR5 will have to be explicitly labeled as the ECC variety.
 

TLDR, if the DIMM isn't labeled as supporting ECC, it's not true ECC all the way through to the CPU.

[Fnige]

1 hour ago, kalymol said:

It is also expected to reach over 10,000 MHz!!!

Wasnt that gigatransfers?

 

Though id expect it to double DDR4 like usual so 10ghz is definitely possible, just probably high end

[WhitetailAni]

Just now, SlimyPython said:

Want that gigatransfers?

 

Though id expect it to double DDR4 like usual so 10ghz is definitely possible, just probably high end

10 GT/s.

I doubt it's running at 10000 MHz (at least right now), most likely 10000 MT/s (so 5000 MHz).

Though who knows. Maybe we'll see 10000 MHz RAM.

Imagine that memory bandwidth.

[Orangeator]

5 hours ago, porina said:

ass

Ass, lol.

[porina]

10 hours ago, StDragon said:

Zen 2 does support ECC with select X570 boards from Gigabyte and ASRock (such as the X570 Taichi)

The only support that matters is from AMD. If AMD doesn't say it is supported, it isn't supported regardless what mobo makers say. Or more correctly, it is unofficial support from mobo makers, in a similar way mobos support ram speeds above the CPU supported speeds. It might or might not work as expected, and is not something you want to say if you really care about having ECC.

 

10 hours ago, StDragon said:

TLDR, if the DIMM isn't labeled as supporting ECC, it's not true ECC all the way through to the CPU.

Hence the differentiation between chip level ECC and module level ECC. Chip level is a basic feature of DDR5 so everyone can enjoy it. Module level will still be a separate option for those who really need it.

[Kisai]

On 4/26/2021 at 8:36 AM, Sauron said:

I just hope this drives DDR4 prices down  

Nah, it's very likely all the DDR4 stock will dry up once the memory manufacturers switch over to DDR5, and the stuff that will disappear first is the specialty memory.

 

I'm not even running this at XMP, given the XMP and JEDEC #7 aren't massively far apart. It's a non-K CPU, and 4 modules, so getting it to boot at XMP isn't recommended.

 

After specialty memory disappears (anything that has an XMP profile frequency higher than the CPU officially supports) then the small modules will disappear, leaving only, 64GB (2 modules) or 128GB ( 4 modules) kits. Why bother building the cheaper slow memory still if nobody is buying it, they'll just continue to build what there are still being OEM machines demand for.

 

There will still be laptop memory for at least another processor generation as the U/Y parts use LPDDR type memory, and even new stuff was still coming with LPDDR3 still. As long as an OEM is still using DDR4, there will still be DDR4 memory available for a while. When I recycled all the old memory (DDR1, DDR2, and DDR3) at the office, the most common stuff was Hynix and Samsung.

[StDragon]

14 hours ago, porina said:

The only support that matters is from AMD. If AMD doesn't say it is supported, it isn't supported regardless what mobo makers say. Or more correctly, it is unofficial support from mobo makers, in a similar way mobos support ram speeds above the CPU supported speeds. It might or might not work as expected, and is not something you want to say if you really care about having ECC.

Per AMD.

 

"ECC is not disabled. It works, but not validated for our consumer client platform.

 

Validated means run it through server/workstation grade testing. For the first Ryzen processors, focused on the prosumer/gaming market, this feature is enabled and working but not validated by AMD. You should not have issues creating a whitebox homelab or NAS with ECC memory enabled."

 

Supported insomuch as being enabled, just not validated for enterprise use as they won't stand behind how OEMs implement it into their products. Not sure how to read this approach honestly. I mean, it's not just-so-happens to run ECC (unregistered DIMMS only); it was specifically engineered into the chip. To my knowledge the I/O die for Ryzen is different than Thread Ripper and Epic, so I don't see this as being an inherited feature. Why go through all that trouble? For 99% of the Intel Core series, that function doesn't even exist in hardware. Intel specifically segments the enterprise market with the line in the sand being a function of ECC. I can only surmise that AMD wants their CPUs in all segments including small workstation use while keeping their distance from Consumer chips being used for enterprise. Essentially, they want their cake and eat it too.

 

14 hours ago, porina said:

Chip level is a basic feature of DDR5 so everyone can enjoy it. Module level will still be a separate option for those who really need it.

Bit-flips occur from one of two primary modes: First being completely random cosmic ray or material defect in a transistor. Second being memory timing issues between the CPU and DIMM. DDR5 inherently solves the first problem not not the second.

[porina]

10 hours ago, StDragon said:

Supported insomuch as being enabled, just not validated for enterprise use as they won't stand behind how OEMs implement it into their products.

Don't disagree with that. My position remains, if you really need ECC, you probably should be going for a fully validated system. 

 

10 hours ago, StDragon said:

Bit-flips occur from one of two primary modes: First being completely random cosmic ray or material defect in a transistor. Second being memory timing issues between the CPU and DIMM. DDR5 inherently solves the first problem not not the second.

In the past I had asked a question but I'm not sure if anyone has an answer for it. In the event of a bad bit coming from ram, what is the proportion due to corruption in storage, or on transfer?

 

The reality is the vast majority of us run without any ECC in ram, often at speeds above standards. Neither are a big problem currently, but with the combination of increasing speed and capacity, it may become more so in future.

[leadeater]

10 hours ago, StDragon said:

it was specifically engineered into the chip. To my knowledge the I/O die for Ryzen is different than Thread Ripper and Epic, so I don't see this as being an inherited feature.

It is, Ryzen/Ryzen Pro has it's own IOD. Ryzen Pro has the validated ECC support. I haven't looked at how easy it is to buy Ryzen Pro though, you know as in not as part of a built system.

[StDragon]

4 hours ago, porina said:

In the past I had asked a question but I'm not sure if anyone has an answer for it. In the event of a bad bit coming from ram, what is the proportion due to corruption in storage, or on transfer?

 

The reality is the vast majority of us run without any ECC in ram, often at speeds above standards. Neither are a big problem currently, but with the combination of increasing speed and capacity, it may become more so in future.

You might find this 2008 Google study to be informative. https://research.google/pubs/pub35162.pdf

 

"In this paper, we analyze measurements of memory errors in a large fleet of commodity servers over a period of 2.5 years. The collected data covers multiple vendors, DRAM capacities and technologies, and comprises many millions of DIMM days. The goal of this paper is to answer questions such as the following: How common are memory errors in practice? What are their statistical properties? How are they affected by external factors, such as temperature and utilization, and by chip-specific factors, such as chip density, memory technology and DIMM age?"

 

"We found the incidence of memory errors and the range of error rates across different DIMMs to be much higher than previously reported. About a third of machines and over 8% of DIMMs in our fleet saw at least one correctable error per year. Our per-DIMM rates of correctable errors translate to an average of 25,000–75,000 FIT (failures in time per billion hours of operation) per Mbit and a median FIT range of 778 – 25,000 per Mbit (median for DIMMs with errors), while previous studies report 200-5,000 FIT per Mbit. The number of correctable errors per DIMM is highly variable, with some DIMMs experiencing a huge number of errors, compared to others. The annual incidence of uncorrectable errors was 1.3% per machine and 0.22% per DIMM"

 

Other notable findings include discoveries that temperature has a surprising lesser impact than normally assumed (but it does nonetheless on extreme temp thresholds). Also that if a DIMM has had an error in the past, there's a probability that it will have additional incidences in the future. Oh, and I found it rather surprising that density didn't' have much of an effect. If each transistor is made up of fewer atoms as the lithography gets smaller, I would have intuitively thought a charged particle (cosmic ray) would have made them more sensitive to a bit-flip. Maybe that's still the case as it's already a 12 years old study, but I would love to see a follow up to this.

 

It's ultimately up to consumer choice, but IMHO ECC memory should have been an industry standard for all computing devices. It would have prevented a lot of kernel panics and other software anomalies. Also would have drastically reduced bit-rot as corrupted data in RAM gets committed back to disk. That is after all why ECC is recommended for storage devices such as SANs.

[igormp]

On 4/26/2021 at 9:36 AM, PianoPlayer88Key said:

My big concern with DDR5 isn't so much getting much faster memory (although that would be nice too); but I really need much higher capacities.

I feel you

 

Luckily I can still upgrade to 128gb (which I'll likely do until the end of this year), should be enough until DDR5 is more standardized and high-density sticks become available.

On 4/26/2021 at 4:37 PM, porina said:

Good luck with that. If you want the lower cost of a consumer level system it seems unlikely you'll get beyond 128GB (4x32GB), maybe 256GB if DDR5 steps up to 64GB modules. I don't see them going above 4 slots still. You'll probably have to look at HEDT level for 8 slots.

64gb consumer sticks should be a thing without problems. In theory, you could have 4x more density (up to 128gb per stick with dual rank).

[StDragon]

13 minutes ago, igormp said:

Luckily I can still upgrade to 128gb (which I'll likely do until the end of this year), should be enough until DDR5 is more standardized and high-density sticks become available.

64gb consumer sticks should be a thing without problems. In theory, you could have 4x more density (up to 128gb per stick with dual rank).

At the moment, DDR4 consumer CPUs (both AMD Ryzen and Intel Core series) max out at 128GB addressable memory.

 

With DDR5 systems, will both AMD and Intel raise that limit, or will they kneecap it to force consumers toward Thread Ripper, Epic, and Xeon that need more than 128GB? Market segmentation.

[igormp]

6 minutes ago, StDragon said:

At the moment, DDR4 consumer CPUs (both AMD Ryzen and Intel Core series) max out at 128GB addressable memory.

They max at 128gb because you can only have 4 sticks of unbuffered ECC, which cap out at 32gb for each stick. Those same sticks should go up to 128gb on DDR5.

7 minutes ago, StDragon said:

With DDR5 systems, will both AMD and Intel raise that limit

Currently, it's not an artificial limit, it's an actual lack of hw support for registered DIMMs on those platforms. If they were to limit the new platforms to the same 128gb, then you'd need an artificial limit, which would cause a major backlash.

Threadripper also didn't support registered DIMMs until the latest TR Pro, which required a new socket.

[porina]

46 minutes ago, StDragon said:

You might find this 2008 Google study to be informative. https://research.google/pubs/pub35162.pdf

Thanks, I had seen that before, but from memory it was tough reading and didn't break it down to answer the question I had on if the errors were in storage or in transfer.

 

 

46 minutes ago, StDragon said:

Other notable findings include discoveries that temperature has a surprising lesser impact than normally assumed (but it does nonetheless on extreme temp thresholds). Also that if a DIMM has had an error in the past, there's a probability that it will have additional incidences in the future.

Kinda makes sense, if the ram has a week spot, that would continue to be a problem. ECC masks fixes problem after it happens, but doesn't prevent it in the first place. I suppose that could also expose you to increased risk of uncorrectable errors if you're already eating into the ability with correctable ones.

 

46 minutes ago, StDragon said:

It's ultimately up to consumer choice, but IMHO ECC memory should have been an industry standard for all computing devices. It would have prevented a lot of kernel panics and other software anomalies. Also would have drastically reduced bit-rot as corrupted data in RAM gets committed back to disk. That is after all why ECC is recommended for storage devices such as SANs.

I still think it comes down to risk vs cost. Imagine if road cars had to go through the same level of scrutiny as aircraft do. Increased levels of checks that everything is in correct working order, better build, it will all cost. What we have is something that is certainly not as good as it could be, but it also doesn't incur that cost. The choice is there for those that need it, and for those that don't, running without is still good enough (for now).

 

17 minutes ago, StDragon said:

At the moment, DDR4 consumer CPUs (both AMD Ryzen and Intel Core series) max out at 128GB addressable memory.

 

With DDR5 systems, will both AMD and Intel raise that limit, or will they kneecap it to force consumers toward Thread Ripper, Epic, and Xeon that need more than 128GB? Market segmentation.

Presuming die densities will increase, it seems logical to follow that maximum module capacities will increase also. I don't know what maximum unbuffered module capacity will be for DDR5. I do recall that when 32GB modules first came out on DDR4, platform compatibility was a problem. I guess it is not so now, but would hope that better defined future limits will be set for DDR5.