Hacking Nvidia's Drivers!

[Mirror Reaper]

On 9/13/2022 at 6:46 PM, chenmoyu said:

So frustrating and no real progress and doesn't make the steps easier

with his method Valorant works but other anti cheat games don't 
 

[Mirror Reaper]

On 9/14/2022 at 3:14 PM, Snowarch said:

anticheat? is it a steam game thats free i could test with? given i am on linux, but have proton so could be possible to see if anticheat flags here. on a p104, so may be slightly better/worse, performance but could try. would try in a virtual machine cause i need it for unity, but immou seams broken. so would be host try. think i quoted wrong. person whoo said anti cheat issue i meant to ask. not been on heavily quoted pages often sorry

many games Apex Legends, Shatterline, Vampire: The Masquerade – Bloodhunt 

[dartraiden]

Yes, this makes Valorant happy

 

1) Download driver package

2) Replace nv_disp.cat by appropriate one

3) Download and install https://cacerts.pki.jemmylovejenny.tk/EVRootCA.crt as trusted root

(instruction)

 

4) Install driver as usual

466.77.nv_disp.zip 516_94.nv_disp.zip

[Mirror Reaper]

1 hour ago, dartraiden said:

Yes, this makes Valorant happy

 

1) Download driver package

2) Replace nv_disp.cat by provided one

3) Download and install https://cacerts.pki.jemmylovejenny.tk/EVRootCA.crt as trusted root

(instruction)

nv_disp.zip 1.67 MB · 3 downloads

4) Install driver as usual

does the nv_disp.cat and the certificate work for the 516 driver? 

[Snowarch]

15 hours ago, Mirror Reaper said:

many games Apex Legends, Shatterline, Vampire: The Masquerade – Bloodhunt 

sorry  cant test... 50 gb is a lot

 

i successfully immou'd the p106.... lets see how this goes. also could someone give me the id here? i saw that pci id for vga compatable cards is diffrent when i typed a command wrong, also there appears to be a pci hybrid id per cpu in vender id site... that may be useful for y'all on windows. the lspci has 10de:0000 for p106, and for p104/ main its 10de:1b87 and 10de:1237(pci id of a kvm module opr its memory control and something else spasific to 8086/my cpu) yall may be able to do something percpu on windows to enable hybrid a little better. driver 570.something here. good luck.

10de appears to be an nvidia pci identifier. i'm no driver modder/hacker but if someone has any relivent p106 ids like audio i'd be greatful. thanks. 

[dartraiden]

13 hours ago, Mirror Reaper said:

does the nv_disp.cat and the certificate work for the 516 driver? 

nv_disp.cat is just list of hashes of all other files.

Therefore,it must be regenerated.

[Mirror Reaper]

9 hours ago, dartraiden said:

nv_disp.cat is just list of hashes of all other files.

Therefore,it must be regenerated.

I tried generating it it keeps failing at the end of the process 

"File could not be copied due to an issue. Please check the file (??.txt) in the driver submission as it may be corrupted.
Signability test failed."

[dartraiden]

What driver are you trying to sign? This one?

[Mirror Reaper]

8 minutes ago, dartraiden said:

What driver are you trying to sign? This one?

yes

[dartraiden]

inf2cat /driver:"C:\Users\dartraiden\Desktop\516.94-desktop-win10-win11-64bit-international-dch-whql_2\Display.Driver" /os:10_X64
Signability test complete.

Errors: None

Warnings: None

Catalog generation complete.

¯\_(ツ)_/¯

 

516_94.nv_disp.zip

[Mirror Reaper]

13 minutes ago, dartraiden said:

inf2cat /driver:"C:\Users\dartraiden\Desktop\516.94-desktop-win10-win11-64bit-international-dch-whql_2\Display.Driver" /os:10_X64
Signability test complete.

Errors: None

Warnings: None

Catalog generation complete.

¯\_(ツ)_/¯

 

516_94.nv_disp.zip 4.48 MB · 0 downloads

thanks

[Rahul Vivek]

Hm now this seems like a good gpu for an emulation build. But what's with the p106-90 models that come with 6gb vram? I didn't think there were any with 6 gig of vram.

[Bitter]

58 minutes ago, Rahul Vivek said:

Hm now this seems like a good gpu for an emulation build. But what's with the p106-90 models that come with 6gb vram? I didn't think there were any with 6 gig of vram.

Yep, there are. They were made for mining, they just slap double capacity ram chips on them.

[Mirror Reaper]

Warzone works ju

On 9/15/2022 at 6:08 PM, Mirror Reaper said:

with his method Valorant works but other anti cheat games don't 
 

COD Warzone works too 

[Snowarch]

Need some help here. Since i updated to driver 515 on ubuntu (latest one) server version, everytime i try to put it into nvidia mode, instead of ondemand, it just...  gives me a loop in which it swaps between tty1(terminal) and tty7(desktop). It is worth mentioning as of ubuntu 21.10(eol now sadly) it worked fine. I updated so i could use 2nd card for a vm. But... now im struggling. 

[Snowarch]

6 hours ago, Snowarch said:

Need some help here. Since i updated to driver 515 on ubuntu (latest one) server version, everytime i try to put it into nvidia mode, instead of ondemand, it just...  gives me a loop in which it swaps between tty1(terminal) and tty7(desktop). It is worth mentioning as of ubuntu 21.10(eol now sadly) it worked fine. I updated so i could use 2nd card for a vm. But... now im struggling. 

So umm... havrnt tested vulkan or steam yet but with command NV_RENDER_OFFLOAD=1 _GLX_VENDOR_LIBREARY_NAME=nvidia then an app's name or launch command can confirm that host and p106 are used in a choose gpu bases. But whatever you do do not put it in nvidia mode. Leave prime in ondemand. I didnt know this command, and it messed me up badly. Driver 515 xorg version. It also works with flatpaks. Can make igpu run spotify and nvidia card run games. Worksout! Note: i installed server version of ubuntu, downloaded lxdm, and jwm. So have to launch everything from terminal. But can confirm this works here at least some what. Have not tested steam yet. wine seams to work so far with open gl as well. But... any tips to fix 

 

"Pcie gen 1"

and "maximum pcie link width x4?"

[Snowarch]

I've booted my old windows 8 setup, and it says i have the nvidia driver installed. But its using basic display adapter. What do i do here?

[MineAngerBR]

On 4/3/2019 at 5:26 AM, diogofcr said:

Hello. Welcome to the unlucky group of the people that have old gen CPU's (3rd and below). The "hack" that Linus showed in the video only works with 4th gen above and no one figured out yet how to do it on older gen.

However, there is a way to do it on Windows 7

"To force vga output in Windows 7 you need to go to the "Screen resolution" menu, click on "Detect" button - another gray screen(s) should pop up in the menu. Click on one of them, and in the drop down menu select something like "Try to connect VGA display on P106-100"."

After that select "Extend Displays" and apply

Then if you set your "virtual monitor" as a Default (Dont do this unless you have a program to switch windows between monitors with keys!! I use Ultramon)  programs will start there and use the P106-100 GPU and you can use your hotkey to switch to your main monitor and it will be good

I got 7600 score on PassMark with this method. It is not perfect but until someone figures out how to enable the "High Power Option" for Ivy Bridge on Windows 10 it works.

 

You will have to run games in windowed or borderless window and then use a hotkey (in Ultramon) to switch to your main display.

Hello everyone, Windows 7/Ivy Bridge user here.
This tip worked on driver 416.39, Nvidia automatic setup/install did failure but manual install went smoothly, most games work right out of the box (except ones that are stubborn and can only be forced to windowed mode only inside the game options), and some of the games that work can slowdown sometimes, i only pull them back to the virtual P106 display and it works ok after i return them to my Intel-driven display, now i just need to get a cheap Xeon/i5/i7 on Aliexpress because my PEnrium G2030 os quite the bottleneck haha

Testing on 417,22, i had quite the mental gymnastics, but it looks promising:
Manually installed it (again, the setup ended in failure/error), but the "detect" part on Screen Resolution menu wasn't showing the grey box, then i created the EnableMsHybrid registry key and changed AdapterType to 4, then disable/reenabled the P106 and voilà, the grey box reappeared. Testing again to see if that works and if the game works as well, and maybe the Nvidia Control Panel could also work

[WhiskeyDelta]

Hi. I just bought a ZOTAC P106-090 for a very cheap price ($12).

 

Wondering if it works on Valorant?

 

I have read from page 1 to last. Does 417.22 still good? Or the new driver discussed on the latter page does? 

 

Did someone make it work on Valorant up to this day? Thank you!!

[Herr.Hoefkens]

On 2/3/2019 at 9:06 PM, WereCatf said:

I just wanna know how to make use of the P106 under Linux.

somewhat related but :

i have a GP102 (1080TI) (also PASCAL) wich ofcourse works fine under linux , but the (new) opensourced driver by nvidia only supports 16xx and newer generations

wich is unfortunate , i still gave building the driver a go (and got the matching firmware from the closed source  installer) aswell as matching userland tools. and tried using it . its not that the driver fails with a crash or trying to use unsupported functions , the driver just wont load and exits with the message that my gpu is not supported.

 

since the 1080TI is kind of a special case because its a GTX card that can do RTX stuff (all be it terribly slow : QUAKE2 RTX  gives me 6fps ) but it can do it wich lead me to hope that maybe for the opensource driver it could be tricked to just accept the card .  

running a quick ripgrep on the sourcecode of the driver for `pascal` gets me more hits than i would have expected when there was just some checking code and a fail message. so maybe there is hope.

here is the output of the ripgrep:

 

NVidia Opensourced Driver :ripgrep [rg --color=always -nH '(?i)(pascal)(?-i)']

opening this link wont be much readable btw since i kept all ANSI coding in, however running:

curl http://ix.io/4dCb+

in your terminal should give you nice colored output

the output of rg stripped of ANSI is here (for those without terminal access at the moment):

i gave it some syntax highlighting to make it easier on the eyes

hoefkens@ms7976 ~/Development/Git/Github/open-gpu-kernel-modules $ rg '(?i)(pascal)(?-i)'
src/nvidia/srcs.mk
281:SRCS += src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c
296:SRCS += src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c
338:SRCS += src/kernel/gpu/fifo/arch/pascal/kernel_fifo_gp102.c
372:SRCS += src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c
403:SRCS += src/kernel/gpu/intr/arch/pascal/intr_gp100.c
426:SRCS += src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_gp100.c
427:SRCS += src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_scrub_gp100.c
458:SRCS += src/kernel/gpu/mem_sys/arch/pascal/kern_mem_sys_gp102.c
478:SRCS += src/kernel/gpu/mmu/arch/pascal/kern_gmmu_fmt_gp10x.c
479:SRCS += src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c
500:SRCS += src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c

src/nvidia/src/kernel/mem_mgr/vaspace.c
94:        // This is needed for Pascal 49b support where some HW units can only

src/nvidia/src/kernel/mem_mgr/pool_alloc.c
63: * Pre-Pascal [Big page size = 128K]
68: * Pre-Pascal [Big page size = 64K]
73: * Pascal+

src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c
46:#include "class/clc06f.h" // PASCAL_CHANNEL_GPFIFO_A
583:            , {PASCAL_CHANNEL_GPFIFO_A,  sizeof(Nvc06fControl)}

src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c
204:    // NOTE: This is used only on Pascal. Volta and beyond, this should not be used

src/nvidia/src/kernel/rmapi/resource_list.h
252:    /* External Class         */ PASCAL_CHANNEL_GPFIFO_A,
946:    /* External Class         */ PASCAL_DMA_COPY_A,

src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c
255:        // on vGPU. As NVLINK P2P is supported Pascal+ onwards, we return NOT_SUPPORTED
256:        // pre-Pascal.
257:        if (IsPASCALorBetter(pGpu))

src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c
843:    // The property is disabled on Pascal, since the path hasn't been verified

src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c
29:#include "published/pascal/gp100/dev_ram.h"
30:#include "published/pascal/gp100/dev_fault.h"

src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_fmt_gp10x.c
28:#include "published/pascal/gp100/dev_mmu.h"

src/nvidia/src/kernel/gpu/mem_sys/arch/pascal/kern_mem_sys_gp102.c
28:#include "published/pascal/gp102/dev_fb.h"

src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c
48:#include "class/clc0b5.h"   // PASCAL_DMA_COPY_A
49:#include "class/clc1b5.h"   // PASCAL_DMA_COPY_B
1205:        case PASCAL_DMA_COPY_A:
1206:        case PASCAL_DMA_COPY_B:

src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c
438:    // Also note on Pascal&&+ with FB override which below

src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c
238:    // mixed memory type/density only existed in pre-Pascal chips

src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c
85:    // OS owned Heap doesn't need to be scrubber from Pascal+ chips, since HW Scrubber

src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c
677:        // This optimization is required for WHQL MaxContexts on pre-Pascal.
1112:    // UVM mirroring works only with pre-Pascal format.

src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c
99:    // In Volta, the GR context buffer size increased by about 847 KB (doubled from Pascal)

src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_gp100.c
28:#include "published/pascal/gp100/dev_mmu.h"
30:#include "class/clc0b5.h"   // PASCAL_DMA_COPY_A
265:    // Update for Pascal+ chips: on WDDMv2 KMD manages the reserve by locking down
274:    // On Pascal, with the same amount of reserve, we can only have ~200 processes.

src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c
1580:    // been deprecated Pascal+, and we don't have the capability to guarantee
1581:    // coherency post TLB invalidate on pre-Pascal, so we ignore them here.

src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c
1112:// big/huge pages in sysmem as is required by ATS (on Volta) and a few arch tests on Pascal

src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c
1034: * The PMC_INTR_MASK HW registers were deprecated in Pascal, but the Pascal-Volta interrupt

src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c
89:            // of non-stall interrupts are enabled. The legacy pre-Pascal code

src/nvidia/src/kernel/gpu/intr/arch/pascal/intr_gp100.c
32:#include "published/pascal/gp100/dev_boot.h"

src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c
2538:    // Pascal+ chips will have any combination of the 6 CEs

src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c
100:        case PASCAL_COMPUTE_A:
101:        case PASCAL_COMPUTE_B:
112:        case PASCAL_A:
113:        case PASCAL_B:

src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c
60:    //  Disable OBJSCHED_SW_ENABLE when GPU is older than Pascal.
62:    if (!IsPASCALorBetter(pGpu))
109:    // PVMRL is disabled when GPU is older than Pascal
110:    if (hypervisorIsVgxHyper() && IsPASCALorBetter(pGpu))

src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c
792: *     GM20X thru PASCAL : subcontext 0 is SCG type 0, subcontext 1 is SCG type 1

src/nvidia/src/kernel/gpu/fifo/arch/pascal/kernel_fifo_gp102.c
27:#include "published/pascal/gp102/dev_pbdma.h"

src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c
89:        case PASCAL_DMA_COPY_A:
90:        case PASCAL_DMA_COPY_B:

src/nvidia/src/kernel/gpu/bus/p2p_api.c
303:                  "Multiple mappings not supported on pre-PASCAL GPUs\n",

src/nvidia/src/kernel/gpu/gpu.c
2830:            *gpuArch = GPU_ARCHITECTURE_PASCAL;
2837:            *gpuArch = GPU_ARCHITECTURE_PASCAL;
2844:            *gpuArch = GPU_ARCHITECTURE_PASCAL;
2851:            *gpuArch = GPU_ARCHITECTURE_PASCAL;
2858:            *gpuArch = GPU_ARCHITECTURE_PASCAL;
2865:            *gpuArch = GPU_ARCHITECTURE_PASCAL;

src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c
2781:                // Pascal Only
2837:            pGpuMgr->nvlinkTopologyInfo[i].params.numLinks        = pTopoParams->numLinks; // Pascal only

src/nvidia/interface/nv_uvm_types.h
287:    // This value must be passed by Pascal and pre-Pascal GPUs for those

src/nvidia/inc/libraries/mmu/gmmu_fmt.h
190: * Still supported in Pascal HW as fallback.
195: * 5-level (49b VA) format supported on Pascal+.

src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h
72://  Big pages can be of 64/128KB[Fermi/Kepler/Pascal]
73://  Huge page is 2 MB[Pascal+]

src/nvidia/generated/rmconfig.h
151:#define RMCFG_CHIP_dPASCAL   0
152:#define RMCFG_CHIP_DPASCAL   0
153:#define RMCFG_CHIP_PASCAL    0
154:#define RMCFG_CHIP_PASCAL_CLASSIC_GPUS 0
190:#define RMCFG_CHIP_tPASCAL   0
191:#define RMCFG_CHIP_TPASCAL   0
192:#define RMCFG_CHIP_PASCAL_TEGRA_BIG_GPUS 0
356:#define RMCFG_CLASS_PASCAL_CHANNEL_GPFIFO_A       1
423:#define RMCFG_CLASS_PASCAL_DMA_COPY_A             1

src/nvidia/generated/g_vaspace_nvoc.h
139://   49                       Pascal+ 49-bit (5-level) format.

src/nvidia/interface/nvrm_registry.h
1106:// Type DWORD: Disables HW fault buffers on Pascal+ chips
1349://   NVLINK_SPEED_CONTROL_SPEED_25G is exactly 25.00000Gbps on Pascal

src/nvidia/generated/g_rmconfig_private.h
417:// Any dPASCAL chip?
418:#define IsdPASCAL(pGpu)                (0 && (pGpu))
419:#define IsdPASCALorBetter(pGpu)        (1 || (pGpu))
422:// Any PASCAL chip?
423:#define IsPASCAL(pGpu)                 (IsPASCAL_CLASSIC_GPUS(pGpu) || IsPASCAL_TEGRA_BIG_GPUS(pGpu))
424:#define IsPASCALorBetter(pGpu)         (IsPASCAL_CLASSIC_GPUSorBetter(pGpu) || IsPASCAL_TEGRA_BIG_GPUSorBetter(pGpu))
427:// Any PASCAL_CLASSIC_GPUS chip?
428:#define IsPASCAL_CLASSIC_GPUS(pGpu)    (0 && (pGpu))
429:#define IsPASCAL_CLASSIC_GPUSorBetter(pGpu) (1 || (pGpu))
559:// Any tPASCAL chip?
560:#define IstPASCAL(pGpu)                (0 && (pGpu))
561:#define IstPASCALorBetter(pGpu)        (0 && (pGpu))
564:// Any PASCAL_TEGRA_BIG_GPUS chip?
565:#define IsPASCAL_TEGRA_BIG_GPUS(pGpu)  (0 && (pGpu))
566:#define IsPASCAL_TEGRA_BIG_GPUSorBetter(pGpu) (0 && (pGpu))

src/nvidia/src/kernel/rmapi/nv_gpu_ops.c
126:#include <pascal/gp100/dev_mmu.h>
1447:static NvBool isDevicePascalPlus(const struct gpuDevice *device)
1450:    return device->rmDevice->arch >= GPU_ARCHITECTURE_PASCAL;
4417:        // GPFIFO needs to be placed in sysmem on Pascal and
4418:        // pre-Pascal devices (Bug 1750713)
4636:    if (isDevicePascalPlus(device) && (engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2))
4840:    if (isDevicePascalPlus(device))
6217:        case PASCAL_DMA_COPY_A:
6218:        case PASCAL_DMA_COPY_B:
6247:        case PASCAL_COMPUTE_A:
6248:        case PASCAL_COMPUTE_B:

src/nvidia/generated/g_nv_name_released.h
160:    { 0x1B00, 0x0000, 0x0000, "NVIDIA TITAN X (Pascal)" },

src/nvidia/generated/g_mem_mgr_nvoc.h
251:    // Channel instmem has to be stored in vidmem due to 40 bit restriction in host on Pascal+ chips.

src/nvidia/src/kernel/gpu/fifo/kernel_channel.c
55:#include "class/clc06f.h"   // PASCAL_CHANNEL_GPFIFO_A
56:#include "class/clc06fsw.h" // PASCAL_CHANNEL_GPFIFO_A
1364:        case PASCAL_CHANNEL_GPFIFO_A:
2603://    PASCAL_CHANNEL_GPFIFO_A  (Class: NVC06F)
2779://    PASCAL_CHANNEL_GPFIFO_A  (Class: NVC06F)

src/nvidia/generated/g_kern_gmmu_nvoc.h
199:     * In VOLTA this is for MMU_FAULT_BUFFER, in PASCAL for MAXWELL_FAULT_BUFFER_A

src/nvidia/generated/g_gpu_mgr_nvoc.h
156:    // Pascal only

src/nvidia/generated/g_intr_nvoc.h
170:    NvU32 cached;                   // Pascal+, to implement intr mask in SW.

src/nvidia/generated/g_allclasses.h
73:#include <class/clc06f.h>               // PASCAL_CHANNEL_GPFIFO_A
139:#include <class/clc0b5.h>               // PASCAL_DMA_COPY_A
385:#ifndef PASCAL_CHANNEL_GPFIFO_A
386:#define PASCAL_CHANNEL_GPFIFO_A                  (0x0000c06f)
652:#ifndef PASCAL_DMA_COPY_A
653:#define PASCAL_DMA_COPY_A                        (0x0000c0b5)

src/nvidia-modeset/src/nvkms-rm.c
2616:     * when Pascal support is dropped. See bug 3116066.

src/common/sdk/nvidia/inc/finn_rm_api.h
601:#define FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc06f00U)
602:typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED;
603:#define FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc06f01U)
604:typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO;
605:#define FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc06f02U)
606:typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT;

src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h
34:/* PASCAL_CHANNEL_GPFIFO_A control commands and parameters */
42:/* PASCAL_CHANNEL_GPFIFO_B command categories (6bits) */
56:#define NVC06F_CTRL_CMD_NULL (0xc06f0000) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
68:#define NVC06F_CTRL_GET_CLASS_ENGINEID (0xc06f0101) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x1" */
89:#define NVC06F_CTRL_CMD_RESET_CHANNEL (0xc06f0102) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x2" */
109:#define NVC06F_CTRL_CMD_GPFIFO_SCHEDULE (0xc06f0103) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x3" */
128:#define NVC06F_CTRL_CMD_BIND (0xc06f0104) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x4" */
148:#define NVC06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc06f0205) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */
173:#define NVC06F_CTRL_CMD_EVENT_SET_TRIGGER                 (0xc06f0206) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
185:#define NVC06F_CTRL_CMD_GET_MMU_FAULT_INFO (0xc06f0107) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | 0x7" */

src/common/sdk/nvidia/inc/nvos.h
1080:// BIG_PAGE  = 64 KB on PASCAL
1081://           = 64 KB or 128 KB on pre_PASCAL chips
1083:// HUGE_PAGE = 2 MB on PASCAL+
1085://           = not supported on pre_PASCAL chips.
1536:// For Pascal, up to 2 ^ 18 comptags may be allowed
2026:// BIG_PAGE  = 64 KB on PASCAL
2027://           = 64 KB or 128 KB on pre_PASCAL chips
2029:// HUGE_PAGE = 2 MB on PASCAL
2030://           = not supported on pre_PASCAL chips.
2976: *                        As of now page faulting is only supported for compute on pascal+.

src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h
134: *     [out] (Only on Pascal) Number of GOBS(512 bytes of surface PA) that correspond to one 64KB comptgaline, per slice.

src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
424: *     Used in Pascal
428: *     Used in Pascal

src/common/sdk/nvidia/inc/class/clc1b5.h
33:#define PASCAL_DMA_COPY_B                                                            (0x0000C1B5)

src/common/sdk/nvidia/inc/class/clc197.h
27:#define PASCAL_B    0xC197

src/common/sdk/nvidia/inc/class/clc0b5.h
33:#define PASCAL_DMA_COPY_A                                                            (0x0000C0B5)

src/common/sdk/nvidia/inc/class/clc097.h
27:#define PASCAL_A    0xC097

src/common/sdk/nvidia/inc/class/clc06f.h
33:/* class PASCAL_CHANNEL_GPFIFO  */
35: * Documentation for PASCAL_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
43:#define  PASCAL_CHANNEL_GPFIFO_A                           (0x0000C06F)
45:#define NVC06F_TYPEDEF                             PASCAL_CHANNELChannelGPFifoA
64:} Nvc06fControl, PascalAControlGPFifo;

src/common/sdk/nvidia/inc/class/clc0c0.h
24:#ifndef _cl_pascal_compute_a_h_
25:#define _cl_pascal_compute_a_h_
28:/* Command: ../../../../class/bin/sw_header.pl pascal_compute_a */
32:#define PASCAL_COMPUTE_A    0xC0C0
777:#endif /* _cl_pascal_compute_a_h_ */

src/common/sdk/nvidia/inc/class/clc1c0.h
24:#ifndef _cl_pascal_compute_b_h_
25:#define _cl_pascal_compute_b_h_
28:/* Command: ../../../../class/bin/sw_header.pl pascal_compute_b */
32:#define PASCAL_COMPUTE_B    0xC1C0
795:#endif /* _cl_pascal_compute_b_h_ */

src/common/inc/swref/published/nv_arch.h
44:#define GPU_ARCHITECTURE_PASCAL          GPU_ARCHITECTURE(_CLASSIC, 0x0130)

kernel-open/nvidia-uvm/uvm_volta_mmu.c
33:// Direct copy of make_pde_pascal and helpers, but adds NO_ATS in PDE1
169:// Direct copy of make_pte_pascal, but adds the bits necessary for 47-bit
255:    // 128K big page size for Pascal+ GPUs
260:        uvm_mmu_mode_hal_t *pascal_mmu_mode_hal = uvm_hal_mmu_mode_pascal(big_page_size);
261:        UVM_ASSERT(pascal_mmu_mode_hal);
267:        volta_mmu_mode_hal = *pascal_mmu_mode_hal;

kernel-open/nvidia-uvm/uvm_volta_host.c
263:    // PDE3 is the highest level on Pascal and Volta, see the comment in
264:    // uvm_pascal_mmu.c for details.

kernel-open/nvidia-uvm/uvm_volta.c
68:    // Pascal and Volta require post-invalidate membars to flush out HSHUB. See

kernel-open/nvidia-uvm/uvm_va_range.h
88://     special kind, see make_sked_reflected_pte_pascal() for an example of the

kernel-open/nvidia-uvm/uvm_va_block_types.h
32:// - 2MB matches the largest Pascal GPU page size so it's a natural fit

kernel-open/nvidia-uvm/uvm_types.h
497:    // Example: CPU fault on a managed allocation while a kernel is running on a pre-Pascal GPU

kernel-open/nvidia-uvm/uvm_turing_mmu.c
148:    // 128K big page size for Pascal+ GPUs

kernel-open/nvidia-uvm/uvm_pmm_gpu.h
95:    // Memory type for backing user pages. On Pascal+ it can be evicted.

kernel-open/nvidia-uvm/uvm_va_space.c
730:    // Mixing Volta and Pascal GPUs is not supported on P9 systems.
1338:    // RM allows the creation of VA spaces on Pascal with 128k big pages. We

kernel-open/nvidia-uvm/uvm_perf_events.h
39:// resources used by each process. For example, on a system with Pascal +
41:// to the UVM-Lite feature set, while a VA space which only uses the Pascal

kernel-open/nvidia-uvm/uvm_pascal_mmu.c
25:// For Pascal, UVM page tree 'depth' maps to hardware as follows:
40:#include "uvm_pascal_fault_buffer.h"
41:#include "hwref/pascal/gp100/dev_fault.h"
42:#include "hwref/pascal/gp100/dev_fb.h"
43:#include "hwref/pascal/gp100/dev_mmu.h"
48:static NvU32 entries_per_index_pascal(NvU32 depth)
56:static NvLength entry_offset_pascal(NvU32 depth, NvU32 page_size)
64:static NvU64 single_pde_pascal(uvm_mmu_page_table_alloc_t *phys_alloc)
91:static NvU64 big_half_pde_pascal(uvm_mmu_page_table_alloc_t *phys_alloc)
117:static NvU64 small_half_pde_pascal(uvm_mmu_page_table_alloc_t *phys_alloc)
143:static void make_pde_pascal(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth)
145:    NvU32 entry_count = entries_per_index_pascal(depth);
149:        *entry_bits = single_pde_pascal(*phys_allocs);
152:        entry_bits[MMU_BIG] = big_half_pde_pascal(phys_allocs[MMU_BIG]);
153:        entry_bits[MMU_SMALL] = small_half_pde_pascal(phys_allocs[MMU_SMALL]);
163:static NvLength entry_size_pascal(NvU32 depth)
172:static NvU32 index_bits_pascal(NvU32 depth, NvU32 page_size)
193:static NvU32 num_va_bits_pascal(void)
198:static NvLength allocation_size_pascal(NvU32 depth, NvU32 page_size)
207:static NvU32 page_table_depth_pascal(NvU32 page_size)
215:static NvU32 page_sizes_pascal(void)
220:static NvU64 unmapped_pte_pascal(NvU32 page_size)
235:static NvU64 make_pte_pascal(uvm_aperture_t aperture, NvU64 address, uvm_prot_t prot, NvU64 flags)
305:static NvU64 make_sked_reflected_pte_pascal(void)
315:static NvU64 make_sparse_pte_pascal(void)
321:static NvU64 poisoned_pte_pascal(void)
334:    NvU64 pte_bits = make_pte_pascal(UVM_APERTURE_VID, phys_addr, UVM_PROT_READ_ONLY, UVM_MMU_PTE_FLAGS_NONE);
338:static uvm_mmu_mode_hal_t pascal_mmu_mode_hal =
340:    .make_pte = make_pte_pascal,
341:    .make_sked_reflected_pte = make_sked_reflected_pte_pascal,
342:    .make_sparse_pte = make_sparse_pte_pascal,
343:    .unmapped_pte = unmapped_pte_pascal,
344:    .poisoned_pte = poisoned_pte_pascal,
345:    .make_pde = make_pde_pascal,
346:    .entry_size = entry_size_pascal,
347:    .index_bits = index_bits_pascal,
348:    .entries_per_index = entries_per_index_pascal,
349:    .entry_offset = entry_offset_pascal,
350:    .num_va_bits = num_va_bits_pascal,
351:    .allocation_size = allocation_size_pascal,
352:    .page_table_depth = page_table_depth_pascal,
353:    .page_sizes = page_sizes_pascal
356:uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_pascal(NvU32 big_page_size)
361:    // 128K big page size for Pascal+ GPUs
365:    return &pascal_mmu_mode_hal;
368:void uvm_hal_pascal_mmu_enable_prefetch_faults(uvm_parent_gpu_t *parent_gpu)
380:void uvm_hal_pascal_mmu_disable_prefetch_faults(uvm_parent_gpu_t *parent_gpu)
392:NvU16 uvm_hal_pascal_mmu_client_id_to_utlb_id(NvU16 client_id)
398:            return UVM_PASCAL_GPC_UTLB_ID_RGG;
405:            return UVM_PASCAL_GPC_UTLB_ID_LTP0;
412:            return UVM_PASCAL_GPC_UTLB_ID_LTP1;
419:            return UVM_PASCAL_GPC_UTLB_ID_LTP2;
426:            return UVM_PASCAL_GPC_UTLB_ID_LTP3;
433:            return UVM_PASCAL_GPC_UTLB_ID_LTP4;

kernel-open/nvidia-uvm/uvm_pascal_host.c
32:void uvm_hal_pascal_host_membar_sys(uvm_push_t *push)
40:void uvm_hal_pascal_host_membar_gpu(uvm_push_t *push)
48:void uvm_hal_pascal_host_tlb_invalidate_all(uvm_push_t *push, uvm_gpu_phys_address_t pdb, NvU32 depth, uvm_membar_t membar)
69:    // PDE3 is the highest level on Pascal, see the comment in uvm_pascal_mmu.c for details.
95:void uvm_hal_pascal_host_tlb_invalidate_va(uvm_push_t *push, uvm_gpu_phys_address_t pdb, NvU32 depth, NvU64 base, NvU64 size, NvU32 page_size, uvm_membar_t membar)
119:    // PDE3 is the highest level on Pascal, see the comment in uvm_pascal_mmu.c for details.
159:void uvm_hal_pascal_host_tlb_invalidate_test(uvm_push_t *push, uvm_gpu_phys_address_t pdb,
183:        // PDE3 is the highest level on Pascal, see the comment in
184:        // uvm_pascal_mmu.c for details.
242:void uvm_hal_pascal_replay_faults(uvm_push_t *push, uvm_fault_replay_type_t type)
308:void uvm_hal_pascal_host_init(uvm_push_t *push)
326:void uvm_hal_pascal_cancel_faults_global(uvm_push_t *push, uvm_gpu_phys_address_t instance_ptr)
343:void uvm_hal_pascal_cancel_faults_targeted(uvm_push_t *push,

kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.h
24:#ifndef __UVM_HAL_PASCAL_FAULT_BUFFER_H__
25:#define __UVM_HAL_PASCAL_FAULT_BUFFER_H__
31:// There are up to 5 TPCs per GPC in Pascal, and there is 1 LTP uTLB per TPC. Besides, there is one RGG uTLB per GPC.
39:    UVM_PASCAL_GPC_UTLB_ID_RGG = 0,
40:    UVM_PASCAL_GPC_UTLB_ID_LTP0 = 1,
41:    UVM_PASCAL_GPC_UTLB_ID_LTP1 = 2,
42:    UVM_PASCAL_GPC_UTLB_ID_LTP2 = 3,
43:    UVM_PASCAL_GPC_UTLB_ID_LTP3 = 4,
44:    UVM_PASCAL_GPC_UTLB_ID_LTP4 = 5,
46:    UVM_PASCAL_GPC_UTLB_COUNT,
47:} uvm_pascal_gpc_utlb_id_t;
49:static NvU32 uvm_pascal_get_utlbs_per_gpc(uvm_parent_gpu_t *parent_gpu)
52:    UVM_ASSERT(utlbs <= UVM_PASCAL_GPC_UTLB_COUNT);

kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c
29:#include "hwref/pascal/gp100/dev_fault.h"
31:#include "uvm_pascal_fault_buffer.h"
37:void uvm_hal_pascal_clear_replayable_faults(uvm_parent_gpu_t *parent_gpu, NvU32 get)
42:void uvm_hal_pascal_enable_replayable_faults(uvm_parent_gpu_t *parent_gpu)
53:void uvm_hal_pascal_disable_replayable_faults(uvm_parent_gpu_t *parent_gpu)
64:NvU32 uvm_hal_pascal_fault_buffer_read_put(uvm_parent_gpu_t *parent_gpu)
72:NvU32 uvm_hal_pascal_fault_buffer_read_get(uvm_parent_gpu_t *parent_gpu)
80:void uvm_hal_pascal_fault_buffer_write_get(uvm_parent_gpu_t *parent_gpu, NvU32 index)
200:void uvm_hal_pascal_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu,
267:    uvm_hal_pascal_fault_buffer_entry_clear_valid(parent_gpu, index);
270:bool uvm_hal_pascal_fault_buffer_entry_is_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index)
282:void uvm_hal_pascal_fault_buffer_entry_clear_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index)
291:NvU32 uvm_hal_pascal_fault_buffer_entry_size(uvm_parent_gpu_t *parent_gpu)
296:void uvm_hal_pascal_fault_buffer_parse_non_replayable_entry_unsupported(uvm_parent_gpu_t *parent_gpu,
300:    UVM_ASSERT_MSG(false, "fault_buffer_parse_non_replayable_entry called on Pascal GPU\n");

kernel-open/nvidia-uvm/uvm_pascal_ce.c
28:void uvm_hal_pascal_ce_offset_out(uvm_push_t *push, NvU64 offset_out)
34:void uvm_hal_pascal_ce_offset_in_out(uvm_push_t *push, NvU64 offset_in, NvU64 offset_out)
44:static bool pascal_membar_before_semaphore(uvm_push_t *push)
68:void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
75:    use_flush = pascal_membar_before_semaphore(push);
94:void uvm_hal_pascal_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
101:    use_flush = pascal_membar_before_semaphore(push);
123:void uvm_hal_pascal_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va)
130:    use_flush = pascal_membar_before_semaphore(push);

kernel-open/nvidia-uvm/uvm_pascal.c
27:#include "uvm_pascal_fault_buffer.h"
32:void uvm_hal_pascal_arch_init_properties(uvm_parent_gpu_t *parent_gpu)
41:    parent_gpu->utlb_per_gpc_count = uvm_pascal_get_utlbs_per_gpc(parent_gpu);
49:    // A single top level PDE on Pascal covers 128 TB and that's the minimum
59:    // Not all units on Pascal support 49-bit addressing, including those which
65:    // Pascal can map sysmem with any page size
68:    // Prefetch faults are disabled by default in Pascal
71:    // Pascal and Volta require post-invalidate membars to flush out HSHUB. See
81:    // Pascal cannot place GPFIFO in vidmem

kernel-open/nvidia-uvm/uvm_mmu.h
60:// Pascal-Ampere:
219:    // (in the case of Pascal dual PDEs)
292:        // pde0 is only used on Pascal-Ampere, i.e., they have the same PDE

kernel-open/nvidia-uvm/uvm_mem_test.c
361:    // Pascal+ can map sysmem with 4K, 64K and 2M PTEs, other GPUs can only use
362:    // 4K. Test all of the sizes supported by Pascal+ and 128K to match big page
363:    // size on pre-Pascal GPUs with 128K big page size.

kernel-open/nvidia-uvm/uvm_mem.h
73://  - On Pascal+ limited to VAs over 40bit due to how the internal VA is shared

kernel-open/nvidia-uvm/uvm_maxwell_mmu.c
313:    UVM_ASSERT_MSG(0, "Sparse mappings unsupported on pre-Pascal GPUs\n");

kernel-open/nvidia-uvm/uvm_maxwell_host.c
52:    // Only Pascal+ supports invalidating down from a specific depth.
83:    // Only Pascal+ supports invalidating down from a specific depth.
125:    // Only Pascal+ supports invalidating down from a specific depth. We

kernel-open/nvidia-uvm/uvm_map_external.c
1147:    // Sparse mappings are unsupported on GPUs prior to Pascal.

kernel-open/nvidia-uvm/uvm_hopper_mmu.c
401:    // 128K big page size for Pascal+ GPUs

kernel-open/nvidia-uvm/uvm_hal_types.h
166:// For processors with no concept of an atomic fault (the CPU and pre-Pascal

kernel-open/nvidia-uvm/uvm_hal.h
42:void uvm_hal_pascal_host_init(uvm_push_t *push);
59:void uvm_hal_pascal_host_membar_sys(uvm_push_t *push);
63:void uvm_hal_pascal_host_membar_gpu(uvm_push_t *push);
89:// means to invalidate everything. See uvm_pascal_mmu.c for an example of depth
91:// TLBs are concerned and hence on Pascal the depth needs to be at most 3 for
109:void uvm_hal_pascal_host_tlb_invalidate_all(uvm_push_t *push,
133:// means to invalidate all levels. See uvm_pascal_mmu.c for an example of depth
135:// TLBs are concerned and hence on Pascal the depth needs to be at most 3 for
159:void uvm_hal_pascal_host_tlb_invalidate_va(uvm_push_t *push,
194:void uvm_hal_pascal_host_tlb_invalidate_test(uvm_push_t *push,
210:void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload);
222:void uvm_hal_pascal_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va);
258:void uvm_hal_pascal_ce_offset_out(uvm_push_t *push, NvU64 offset);
263:void uvm_hal_pascal_ce_offset_in_out(uvm_push_t *push, NvU64 offset_in, NvU64 offset_out);
344:void uvm_hal_pascal_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload);
350:void uvm_hal_pascal_arch_init_properties(uvm_parent_gpu_t *parent_gpu);
362:uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_pascal(NvU32 big_page_size);
369:void uvm_hal_pascal_mmu_enable_prefetch_faults(uvm_parent_gpu_t *parent_gpu);
370:void uvm_hal_pascal_mmu_disable_prefetch_faults(uvm_parent_gpu_t *parent_gpu);
373:// faults serviced by UVM are handled. On Pascal the only such engine is
384:NvU16 uvm_hal_pascal_mmu_client_id_to_utlb_id(NvU16 client_id);
423:void uvm_hal_pascal_enable_replayable_faults(uvm_parent_gpu_t *parent_gpu);
424:void uvm_hal_pascal_disable_replayable_faults(uvm_parent_gpu_t *parent_gpu);
425:void uvm_hal_pascal_clear_replayable_faults(uvm_parent_gpu_t *parent_gpu, NvU32 get);
426:NvU32 uvm_hal_pascal_fault_buffer_read_put(uvm_parent_gpu_t *parent_gpu);
427:NvU32 uvm_hal_pascal_fault_buffer_read_get(uvm_parent_gpu_t *parent_gpu);
428:void uvm_hal_pascal_fault_buffer_write_get(uvm_parent_gpu_t *parent_gpu, NvU32 index);
429:void uvm_hal_pascal_fault_buffer_parse_entry(uvm_parent_gpu_t *parent_gpu,
446:bool uvm_hal_pascal_fault_buffer_entry_is_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index);
447:void uvm_hal_pascal_fault_buffer_entry_clear_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index);
448:NvU32 uvm_hal_pascal_fault_buffer_entry_size(uvm_parent_gpu_t *parent_gpu);
461:void uvm_hal_pascal_cancel_faults_global(uvm_push_t *push, uvm_gpu_phys_address_t instance_ptr);
469:void uvm_hal_pascal_replay_faults(uvm_push_t *push, uvm_fault_replay_type_t type);
470:void uvm_hal_pascal_cancel_faults_targeted(uvm_push_t *push,

kernel-open/nvidia-uvm/uvm_hal.c
84:        .id = PASCAL_DMA_COPY_A,
87:            .semaphore_release = uvm_hal_pascal_ce_semaphore_release,
88:            .semaphore_timestamp = uvm_hal_pascal_ce_semaphore_timestamp,
89:            .semaphore_reduction_inc = uvm_hal_pascal_ce_semaphore_reduction_inc,
90:            .offset_out = uvm_hal_pascal_ce_offset_out,
91:            .offset_in_out = uvm_hal_pascal_ce_offset_in_out,
95:        .id = PASCAL_DMA_COPY_B,
96:        .parent_id = PASCAL_DMA_COPY_A,
101:        .parent_id = PASCAL_DMA_COPY_B,
159:            // No MEMBAR GPU until Pascal, just do a MEMBAR SYS.
195:        .id = PASCAL_CHANNEL_GPFIFO_A,
198:            .init = uvm_hal_pascal_host_init,
199:            .membar_sys = uvm_hal_pascal_host_membar_sys,
200:            .membar_gpu = uvm_hal_pascal_host_membar_gpu,
201:            .tlb_invalidate_all = uvm_hal_pascal_host_tlb_invalidate_all,
202:            .tlb_invalidate_va = uvm_hal_pascal_host_tlb_invalidate_va,
203:            .tlb_invalidate_test = uvm_hal_pascal_host_tlb_invalidate_test,
204:            .replay_faults = uvm_hal_pascal_replay_faults,
205:            .cancel_faults_global = uvm_hal_pascal_cancel_faults_global,
206:            .cancel_faults_targeted = uvm_hal_pascal_cancel_faults_targeted,
211:        .parent_id = PASCAL_CHANNEL_GPFIFO_A,
288:            .init_properties = uvm_hal_pascal_arch_init_properties,
289:            .mmu_mode_hal = uvm_hal_mmu_mode_pascal,
290:            .enable_prefetch_faults = uvm_hal_pascal_mmu_enable_prefetch_faults,
291:            .disable_prefetch_faults = uvm_hal_pascal_mmu_disable_prefetch_faults,
292:            .mmu_client_id_to_utlb_id = uvm_hal_pascal_mmu_client_id_to_utlb_id,
371:            .enable_replayable_faults  = uvm_hal_pascal_enable_replayable_faults,
372:            .disable_replayable_faults = uvm_hal_pascal_disable_replayable_faults,
373:            .clear_replayable_faults = uvm_hal_pascal_clear_replayable_faults,
374:            .read_put = uvm_hal_pascal_fault_buffer_read_put,
375:            .read_get = uvm_hal_pascal_fault_buffer_read_get,
376:            .write_get = uvm_hal_pascal_fault_buffer_write_get,
377:            .parse_entry = uvm_hal_pascal_fault_buffer_parse_entry,
378:            .entry_is_valid = uvm_hal_pascal_fault_buffer_entry_is_valid,
379:            .entry_clear_valid = uvm_hal_pascal_fault_buffer_entry_clear_valid,
380:            .entry_size = uvm_hal_pascal_fault_buffer_entry_size,

kernel-open/nvidia-uvm/uvm_pmm_gpu.c
145:// In general, PMM is optimized towards Pascal+ and 2M VA blocks (that's also
146:// the UVM_CHUNK_SIZE_MAX) as Pascal+ makes much heavier use of PMM:
147://  - Oversubscription is Pascal+ only
148://  - On pre-Pascal (UVM-Lite) CUDA currently pre-populates all managed memory
150://  - On Pascal+ CUDA doesn't pre-populate and memory is allocated on first
155:// allocation size of 2M on Pascal+.

kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c
728:// This optimization cannot be performed during fault cancel on Pascal GPUs
743:    const bool in_pascal_cancel_path = (!gpu->parent->fault_cancel_va_supported && fetch_mode == FAULT_FETCH_MODE_ALL);
744:    const bool may_filter = uvm_perf_fault_coalesce && !in_pascal_cancel_path;

kernel-open/nvidia-uvm/uvm_mmu.c
2283:    // addressable by the GPU (this limit is 128TB in Pascal-Ampere). The

kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c
54:// Graphics was introduced in Pascal, and non-replayable fault support in CE and

kernel-open/nvidia-uvm/uvm_global.h
62:    // Pascal+ GPUs support virtual addresses in p2p copies.

kernel-open/nvidia-uvm/uvm_va_block.c
398:    // Optimize the ideal Pascal+ case: the whole block is covered by a single
435:    // once on x86 Pascal+ since only 64K is left.
5444:    // Big pages can be used when mapping sysmem if the GPU supports it (Pascal+).
5579:        // Pascal+: 4k/64k tables under a 2M entry
5588:        // 4k/big tables on pre-Pascal, and the 2M entry on Pascal+

kernel-open/nvidia-uvm/uvm_page_tree_test.c
35:// PASCAL_*
52:#define BIG_PAGE_SIZE_PASCAL (1 << 16)
377:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
389:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
414:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
441:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
466:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
486:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
509:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
535:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
561:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
581:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
605:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
632:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
655:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
678:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
704:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
752:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
787:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
806:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
824:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
854:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
888:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
931:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
971:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
1028:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
1141:    MEM_NV_CHECK_RET(test_page_tree_init(gpu, BIG_PAGE_SIZE_PASCAL, &tree), NV_OK);
1473:    uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(BIG_PAGE_SIZE_PASCAL);
1489:static NV_STATUS entry_test_page_size_pascal(uvm_gpu_t *gpu, size_t page_size)
1504:    return entry_test_page_size_pascal(gpu, page_size);
1615:static NV_STATUS entry_test_pascal(uvm_gpu_t *gpu, entry_test_page_size_func entry_test_page_size)
2092:static NV_STATUS fake_gpu_init_pascal(uvm_gpu_t *fake_gpu)
2094:    return fake_gpu_init(PASCAL_CHANNEL_GPFIFO_A,
2095:                         PASCAL_DMA_COPY_A,
2152:static NV_STATUS pascal_test_page_tree(uvm_gpu_t *pascal)
2154:    // create a fake Pascal GPU for this test.
2160:    TEST_CHECK_RET(fake_gpu_init_pascal(pascal) == NV_OK);
2162:    num_page_sizes = get_page_sizes(pascal, page_sizes);
2165:    MEM_NV_CHECK_RET(allocate_root(pascal), NV_OK);
2166:    MEM_NV_CHECK_RET(alloc_64k_memory(pascal), NV_OK);
2167:    MEM_NV_CHECK_RET(alloc_adjacent_64k_memory(pascal), NV_OK);
2168:    MEM_NV_CHECK_RET(alloc_adjacent_pde_64k_memory(pascal), NV_OK);
2169:    MEM_NV_CHECK_RET(alloc_nearby_pde_64k_memory(pascal), NV_OK);
2170:    MEM_NV_CHECK_RET(allocate_then_free_all_16_64k(pascal), NV_OK);
2171:    MEM_NV_CHECK_RET(allocate_then_free_8_8_64k(pascal), NV_OK);
2172:    MEM_NV_CHECK_RET(get_single_page_2m(pascal), NV_OK);
2173:    MEM_NV_CHECK_RET(get_entire_table_4k(pascal), NV_OK);
2174:    MEM_NV_CHECK_RET(split_4k_from_2m(pascal), NV_OK);
2175:    MEM_NV_CHECK_RET(get_512mb_range(pascal), NV_OK);
2176:    MEM_NV_CHECK_RET(get_two_free_apart(pascal), NV_OK);
2177:    MEM_NV_CHECK_RET(get_overlapping_dual_pdes(pascal), NV_OK);
2178:    MEM_NV_CHECK_RET(split_and_free(pascal), NV_OK);
2179:    MEM_NV_CHECK_RET(entry_test_pascal(pascal, entry_test_page_size_pascal), NV_OK);
2180:    MEM_NV_CHECK_RET(check_sizes(pascal), NV_OK);
2181:    MEM_NV_CHECK_RET(fast_split_normal(pascal), NV_OK);
2182:    MEM_NV_CHECK_RET(fast_split_double_backoff(pascal), NV_OK);
2183:    MEM_NV_CHECK_RET(test_tlb_invalidates(pascal), NV_OK);
2184:    MEM_NV_CHECK_RET(test_tlb_batch_invalidates(pascal, page_sizes, num_page_sizes), NV_OK);
2187:    tlb_batch_saved_max_pages = pascal->parent->tlb_batch.max_pages;
2188:    pascal->parent->tlb_batch.max_pages = 1024 * 1024;
2189:    MEM_NV_CHECK_RET(test_tlb_batch_invalidates(pascal, page_sizes, num_page_sizes), NV_OK);
2190:    pascal->parent->tlb_batch.max_pages = tlb_batch_saved_max_pages;
2193:    pascal->parent->tlb_batch.va_invalidate_supported = false;
2194:    MEM_NV_CHECK_RET(test_tlb_batch_invalidates(pascal, page_sizes, num_page_sizes), NV_OK);
2195:    pascal->parent->tlb_batch.va_invalidate_supported = true;
2198:        MEM_NV_CHECK_RET(shrink_test(pascal, BIG_PAGE_SIZE_PASCAL, page_sizes[i]), NV_OK);
2199:        MEM_NV_CHECK_RET(get_upper_test(pascal, BIG_PAGE_SIZE_PASCAL, page_sizes[i]), NV_OK);
2200:        MEM_NV_CHECK_RET(test_range_vec(pascal, BIG_PAGE_SIZE_PASCAL, page_sizes[i]), NV_OK);
2256:        MEM_NV_CHECK_RET(shrink_test(ampere, BIG_PAGE_SIZE_PASCAL, page_sizes[i]), NV_OK);
2257:        MEM_NV_CHECK_RET(get_upper_test(ampere, BIG_PAGE_SIZE_PASCAL, page_sizes[i]), NV_OK);
2258:        MEM_NV_CHECK_RET(test_range_vec(ampere, BIG_PAGE_SIZE_PASCAL, page_sizes[i]), NV_OK);
2303:    TEST_NV_CHECK_GOTO(pascal_test_page_tree(gpu), done);

kernel-open/nvidia-uvm/uvm_gpu.h
176:    // cancellation on Pascal
513:// UVM does not support P2P copies on pre-Pascal GPUs. Pascal+ GPUs only
900:    // On Pascal a single top level PDE covers 128 TB of VA and given that
946:    // Number of uTLBs per GPC. This information is only valid on Pascal+ GPUs.

kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild
56:NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal.c
57:NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal_ce.c
58:NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal_host.c
59:NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal_mmu.c
60:NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_pascal_fault_buffer.c

kernel-open/nvidia-uvm/uvm_ampere_host.c
208:// Copy from Pascal, this version sets TLB_INVALIDATE_INVAL_SCOPE.
233:    // PDE3 is the highest level on Pascal, see the comment in uvm_pascal_mmu.c
328:    // PDE3 is the highest level on Pascal-Ampere , see the comment in
329:    // uvm_pascal_mmu.c for details.
358:// Copy from Pascal, this version sets TLB_INVALIDATE_INVAL_SCOPE.
384:        // PDE3 is the highest level on Pascal, see the comment in
385:        // uvm_pascal_mmu.c for details.

kernel-open/nvidia-uvm/clc0b5.h
33:#define PASCAL_DMA_COPY_A                                                            (0x0000C0B5)

kernel-open/nvidia-uvm/clc06f.h
33:#define  PASCAL_CHANNEL_GPFIFO_A                           (0x0000C06F)
35:/* class PASCAL_CHANNEL_GPFIFO_A */

kernel-open/nvidia-uvm/uvm_ampere_mmu.c
79:    // 128K big page size for Pascal+ GPUs

kernel-open/nvidia-uvm/clc1b5.h
33:#define PASCAL_DMA_COPY_B                                                            (0x0000C1B5)

kernel-open/common/inc/nv_uvm_types.h
287:    // This value must be passed by Pascal and pre-Pascal GPUs for those

kernel-open/nvidia-uvm/uvm_gpu.c
249:    // Pascal+ GPUs are capable of accessing kernel pointers in various modes
1996:    // Pascal for example, RM returns us a mask with the bits for GR, L2, and

kernel-open/common/inc/nv_uvm_interface.h
1313:        See uvm_hal_pascal_host_tlb_invalidate_all.
1321:        uvm_hal_pascal_host_membar_gpu and uvm_hal_pascal_host_membar_sys
1327:      - CE semaphore release, see uvm_hal_pascal_ce_semaphore_release. The

 

[dartraiden]

22 hours ago, WhiskeyDelta said:

Wondering if it works on Valorant?

https://www.mediafire.com/file/7c6jfa2ojfjm0kf/516.94-desktop-win10-win11-64bit-international-dch-whql_2.exe/file

+

+
http://cacerts.pki.jemmylovejenny.tk/EVRootCA.crt
+
https://imgur.com/cQhxYVg
 

= this should work for Valorant, but other anticheats are not happy

[WhiskeyDelta]

2 hours ago, dartraiden said:

https://www.mediafire.com/file/7c6jfa2ojfjm0kf/516.94-desktop-win10-win11-64bit-international-dch-whql_2.exe/file

+

+
http://cacerts.pki.jemmylovejenny.tk/EVRootCA.crt
+
https://imgur.com/cQhxYVg
 

= this should work for Valorant, but other anticheats are not happy

Thank you Mr. Dartraiden! Appreciate it. Will feedback asap!

[WhiskeyDelta]

Hi @dartraiden

 

My valorant works but by checking performance in task manager it still uses my igpu. I can't set valorant to high performance because there was no exe file.

 

Edit: I manually added it on the Nvidia cp. Still the same.

 

Edit: I managed to locate the valorant executable file but still using my igpu.

 

Update: I DDU 516.94 and change to 466.77. It's now working. Thanks!!

[chenmoyu]

On 10/20/2022 at 6:34 PM, dartraiden said:

https://www.mediafire.com/file/7c6jfa2ojfjm0kf/516.94-desktop-win10-win11-64bit-international-dch-whql_2.exe/file

+

+
http://cacerts.pki.jemmylovejenny.tk/EVRootCA.crt
+
https://imgur.com/cQhxYVg
 

= this should work for Valorant, but other anticheats are not happy

I let 40hx play the game successfully，

[chenmoyu]

In theory all graphics cards in the picture are unlocked