IBM Z

[NumLock21]

Another live blog by Ian Cutress from Anadtech, this time it's all about IBM Z

 

Quote

 

• ... IBM z14 will be interesting
• To clarify, the z series is IBM's mainframe product line
• So this isn't POWER8 or POWER9
• IBM's z-series has central processors and system control chips with integrated fabric and off-compute chip caches
• This is under a 'mainframe' setup, rather than a standard CPU/co-processor setup.
• A lot of mainframes still exist
• Still used in large corporations for transactional data, e.g. credit card has a mainframe involved. 90% of airline booking systems involve mainframes
• Run large databases and large virtualised linux
• Have to make design decisions tailored for those workloads
• z10 was high frequency, z196 had OoO, z13 had SMT and now z14
• The mainframe uses two different chips - the CP (cores and shared L3) and SCP (large L4 and interconnect logic)
• Two clusters of CP chips connect to the SC. Can connect four drawers together
• CP and SC are large chips, 17 layer metal in 14nm SOI
• 10 cores has private 2MB L2-i and 4MB L2-D and 128 MB shared L3
• SC chip has 672MB of L4 and coherency logic
• Up to 24 sockets int he system, 32 TB RAIM protected memory, 40 PCIe lane fanouts, 320 IO cards
• New translation and TLB design over z13, and general pipeline optimations. Changes in instruction set too
• Pauseless garbage collection for Java, single and quad vector precision for crypto
• Register to register arithmatic
• Optimizing for COBOL performance
• Compression acceleration

 

 

Spoiler

 

 

http://www.anandtech.com/show/11750/hot-chips-ibms-next-generation-z14-cpu-mainframe-live-blog-5pm-pt-12am-utc

 

[captain cactus]

5.2 GHz?  

[Coaxialgamer]

3 minutes ago, lots of unexplainable lag said:

5.2 GHz?  

Ibm has actually made faster chips in the past, at 5.5ghz.

[dexT]

3 minutes ago, lots of unexplainable lag said:

5.2 GHz?  

They are WC'd so..

[Dylanc1500]

I love working with the Z series. Some of the most awesome hardware you can deal with.

 

25 minutes ago, lots of unexplainable lag said:

5.2 GHz?  

That's not unheard of with IBM. Z13 had 8 cores with 4MB (2MB instruction/ 2MB data) of l2 cache per core and ran at 5ghz.

[Stefan1024]

37 minutes ago, lots of unexplainable lag said:

5.2 GHz?  

 

33 minutes ago, dexT said:

They are WC'd so..

And 500 watts per CPU

 

[dexT]

Just now, Stefan1024 said:

 

And 500 watts per CPU

 

Yolo

[DocSwag]

43 minutes ago, lots of unexplainable lag said:

5.2 GHz?  

Yup. Super long pipelines allow for really high clocks on these things, albeit at the cost of power and heat.

[Dylanc1500]

3 minutes ago, DocSwag said:

Yup. Super long pipelines allow for really high clocks on these things, albeit at the cost of power and heat.

Fetch 6 and issue 10 per cycle.

[DocSwag]

8 minutes ago, Dylanc1500 said:

Fetch 6 and issue 10 per cycle.

Unfortunately, I do not know enough about comp arch to understand what the hell you just said  

[dexT]

1 minute ago, DocSwag said:

Unfortunately, I do not know enough about comp arch to understand what the hell you just said  

It's instruction queue can fetch 6 instructions per cycle and issue 10 instructions per cycle.

[DocSwag]

1 minute ago, dexT said:

It's instruction queue can fetch 6 instructions per cycle and issue 10 instructions per cycle.

I think I know what that means?

 

The CPU core can fetch 6 instructions every cycle and issue 10 of them to be processed every cycle? But how exactly does it issue more instructions than it can fetch?