HEDT is back - Threadripper 7000 series - Zen 4

[porina]

6 hours ago, leadeater said:

I miss X58 & X79 pricing so much haha

I wasn't active then, but I'd take X99 and X299 pricing.

 

I recall around the time of Skylake's launch, if I should get the 6700k or 5820k. 4 newer faster cores, or 6 slightly older ones I could overclock. CPU and mobo pricing at the time was near enough the same between them.

 

X299 on the lower core count CPUs was also price competitive vs the Intel consumer offerings. I think a lot of hate X299 got was because most of the tech enthusiast media were blinded by the new kid Ryzen, bringing plenty of cores but they weren't that great early on. I guess Intel marketing wasn't going to play the platform over cores game and we lost HEDT.

 

6 hours ago, leadeater said:

@porina FYI if you didn't know The Pro CPUs are supported in the sTRX non-pro motherboards. You just lose out on usable memory channels and PCIe lanes.

Wrong way around for me. Give me all the ram bandwidth. I don't need stupid numbers of cores. I don't play Cinebench competitively any more. Although since it is AMD, the ram bandwidth will get choked internally by Infinity Fabric anyway. If I were to spend 4 figures on a CPU and high 3 digits on a mobo, W-34xx is much more appealing still.

 

6 hours ago, leadeater said:

They kind of do, Pro and HEDT

Thanks, I hadn't seen that slide before now.

 

[Doobeedoo]

Quite the lineup, these will be a hefty boost. I wonder are 3D chips in the works too.

[igormp]

Their performance do look nice

 

[AndreiArgeanu]

At least on the Pro Threadripper side for their 7995WX it does look like they just took the Epyc 9654 and modified it for higher clockspeeds, probably on single/low threaded tasks only. It maybe similar for the rest of the lineup.

 

Although I'm not entirely sure Intel is giving their all on the workstation side. Their Xeon for Workstations or even Scalable lack any kind of efficiency cores. A P+E configuration on a Workstation CPU might work really well, having those high performance cores for single threaded applications and then a lot of efficiency cores maybe even more than AMD that can tackle multi threaded applications. If you don't need all the I/O then Intel's own i9 13900K or 14900k is eating into their workstation processors.

[GOTSpectrum]

10 minutes ago, AndreiArgeanu said:

At least on the Pro Threadripper side for their 7995WX it does look like they just took the Epyc 9654 and modified it for higher clockspeeds, probably on single/low threaded tasks only. It maybe similar for the rest of the lineup.

 

Although I'm not entirely sure Intel is giving their all on the workstation side. Their Xeon for Workstations or even Scalable lack any kind of efficiency cores. A P+E configuration on a Workstation CPU might work really well, having those high performance cores for single threaded applications and then a lot of efficiency cores maybe even more than AMD that can tackle multi threaded applications. If you don't need all the I/O then Intel's own i9 13900K or 14900k is eating into their workstation processors.

If Intel do that AMD would just release a Zen4c part, double core density, their version of an efficiency core, except it's a full fat Zen4 core, just on a denser node library and less cache 

[porina]

5 minutes ago, AndreiArgeanu said:

Although I'm not entirely sure Intel is giving their all on the workstation side. Their Xeon for Workstations or even Scalable lack any kind of efficiency cores.

Look at the mess we had with Alder Lake release. E cores means no AVX-512. 

 

The current WS lineup was also released pretty late. Sapphire Rapids had quite some delays. Its successor Emerald Rapids is round the corner. Wont be a major update but everything extra helps. Sapphire to Emerald Rapids is kinda like Alder to Raptor Lake, so they'll get better power efficiency and/or higher clocks depending on how they push it. The gen after that should get really interesting.

[porina]

5 minutes ago, GOTSpectrum said:

If Intel do that AMD would just release a Zen4c part, double core density, their version of an efficiency core, except it's a full fat Zen4 core, just on a denser node library and less cache 

I wouldn't quite call them full fat, since they're reduced L3 cache like APUs are. Their advantage is the architecture is the same, unlike Intel's P+E arrangement, which probably wont be resolved until AVX10 comes out.

 

As for building a chip with both, my memory isn't so great. Have AMD announced any CPUs with C and c cores officially? It would be a good mix to have both for a general purpose system. For HEDT, WS and server, I don't think they'll split it within a die, but would have to split it per package. e.g. maybe one CCD with C cores, and remaining CCDs with c cores. This could allow a consumer offering of 8C+16c.

[GOTSpectrum]

Just now, porina said:

As for building a chip with both, my memory isn't so great. Have AMD announced any CPUs with C and c cores officially? It would be a good mix to have both for a general purpose system. For HEDT, WS and server, I don't think they'll split it within a die, but would have to split it per package. e.g. maybe one CCD with C cores, and remaining CCDs with c cores. This could allow a consumer offering of 8C+16c.

I don't know if it has been announced officially but Phoenix is slated to have both... 

 

They are full-fat in that they have all the same instructions and transistors as the logic part of the core, but as I said in my post, they do have reduced cache. 

 

E cores a la intel are a different architecture with some instructions missing, hence IMO not "Full-Fat cores" 

[porina]

8 minutes ago, GOTSpectrum said:

They are full-fat in that they have all the same instructions and transistors as the logic part of the core, but as I said in my post, they do have reduced cache. 

I think we agree on the technical side but differ in what we call "full fat". For example, the laptop I'm using right now has a 5800H, which is an 8 core Zen 3 APU but with half the L3 of the full configuration 8 core desktop offerings. I view c cores in the same way. It is cut down. It is not full fat from not having that extra cache.

 

Now you got me thinking of what to call the 3D models. Extra fat?  

[GOTSpectrum]

2 minutes ago, porina said:

I think we agree on the technical side but differ in what we call "full fat". For example, the laptop I'm using right now has a 5800H, which is an 8 core Zen 3 APU but with half the L3 of the full configuration 8 core desktop offerings. I view c cores in the same way. It is cut down. It is not full fat from not having that extra cache.

 

Now you got me thinking of what to call the 3D models. Extra fat?  

hahaha extra-fat

 

I really want them to make 3d cache c cores... because yknow... Although maybe the higher heat density of the c cores is a problem 

[igormp]

39 minutes ago, AndreiArgeanu said:

At least on the Pro Threadripper side for their 7995WX it does look like they just took the Epyc 9654 and modified it for higher clockspeeds, probably on single/low threaded tasks only. It maybe similar for the rest of the lineup.

 

I mean, that's how all threadrippers have been so far lol

40 minutes ago, AndreiArgeanu said:

Their Xeon for Workstations or even Scalable lack any kind of efficiency cores. A P+E configuration on a Workstation CPU might work really well, having those high performance cores for single threaded applications and then a lot of efficiency cores maybe even more than AMD that can tackle multi threaded applications.

You need to pick either all P cores, or all E cores (there are xeon options available this way).

Mixing those is kind of a mess for servers, and those workstation parts are just the same server chip in a different platform.

 

[GOTSpectrum]

2 minutes ago, igormp said:

You need to pick either all P cores, or all E cores (there are xeon options available this way).

Mixing those is kind of a mess for servers, and those workstation parts are just the same server chip in a different platform.

 

That's one advantage of the c cores, they are logically the same cores, WITH LESS CACHE(in caps for @porina) so they act in much the same way for many workloads and thus the scheduling is easier 

[porina]

9 minutes ago, GOTSpectrum said:

That's one advantage of the c cores, they are logically the same cores, WITH LESS CACHE(in caps for @porina) so they act in much the same way for many workloads and thus the scheduling is easier 

I can't hear it. Try bold also?

 

Scheduling is more about getting responsiveness out. Putting time critical things on the fast cores, and the rest on the slower cores. What having the same instruction set gives is the software only needs to optimise for one. To get the absolute most out of P and E cores, more work could be done for each case. I'd argue cache amount is also an optimisation that can be considered. Much software I use will already try to size up work to be done within the cache before moving onto the next bit. 

 

Another potential benefit of C and c vs P & E is that the performance gap between the two types will be narrower. For c cores to be worth it, each would have to do more than half equivalent, whereas E cores might be closer to a quarter of a P.

 

23 minutes ago, GOTSpectrum said:

I really want them to make 3d cache c cores... because yknow... Although maybe the higher heat density of the c cores is a problem 

Is it though? For the same area we have two c cores to one C core, both with their associated caches. Scaling of cache vs logic may not be the same in the redesign, so it doesn't necessarily follow halving the cache amount is half the die area used. Still, I'd assume that per CCD, they'll run the same overall power limit, so average power density is same. If core power density increases or decreases depends on the relative change in core to cache ratio.

 

I think c cores were designed with use cases where cache doesn't matter as much, so it seems counter-intuitive to put more back on it.

[GOTSpectrum]

3 minutes ago, porina said:

I can't hear it. Try bold also?

 

Scheduling is more about getting responsiveness out. Putting time critical things on the fast cores, and the rest on the slower cores. What having the same instruction set gives is the software only needs to optimise for one. To get the absolute most out of P and E cores, more work could be done for each case. I'd argue cache amount is also an optimisation that can be considered. Much software I use will already try to size up work to be done within the cache before moving onto the next bit. 

 

Another potential benefit of C and c vs P & E is that the performance gap between the two types will be narrower. For c cores to be worth it, each would have to do more than half equivalent, whereas E cores might be closer to a quarter of a P.

 

Is it though? For the same area we have two c cores to one C core, both with their associated caches. Scaling of cache vs logic may not be the same in the redesign, so it doesn't necessarily follow halving the cache amount is half the die area used. Still, I'd assume that per CCD, they'll run the same overall power limit, so average power density is same. If core power density increases or decreases depends on the relative change in core to cache ratio.

 

I think c cores were designed with use cases where cache doesn't matter as much, so it seems counter-intuitive to put more back on it.

According to AMD they were made for hyperscalers. Where the "loss" of cache (and small reducing in clocks) is weighed against the increase in core counts. 

 

So they were designed 100% with density in mind, rather than workload imo. 

[williamcll]

The real fun begins when you let it start boosting and the power draw breaks 1100W

[RejZoR]

I wonder how would top end Threadripper with 384MB of L3 cache fare in games if you cut down the threads by disabling cores in BIOS to keep its clocks higher. That would be like 3x the X3D models cache. Would be interesting to see if games scale beyond the X3D cache capacities or not.

[leadeater]

14 hours ago, porina said:

Wrong way around for me. Give me all the ram bandwidth. I don't need stupid numbers of cores.

I know but at least you can have 4 channel memory with a 12 core or 16 core Zen 4 CPU on a cheaper motherboard. That's at least something that might be interesting depending on total system cost. 8 channels is obviously better but maybe not if the motherboard cost is say double that of the TR platform.

 

What I find interesting about it is you're getting a 7950X/ 7900X with double the memory bandwidth, 350W TDP vs 170W, more PCIe lanes and you still get CPU and memory overlocking support. Other than price no down sides, just ahh yea ignore that price haha.

 

14 hours ago, porina said:

If I were to spend 4 figures on a CPU and high 3 digits on a mobo, W-34xx is much more appealing still.

I would probably go with a w5-2455X, 4 channel is fine and actually more PCIe lanes than the TR platform.

[leadeater]

10 hours ago, porina said:

Is it though? For the same area we have two c cores to one C core, both with their associated caches. Scaling of cache vs logic may not be the same in the redesign, so it doesn't necessarily follow halving the cache amount is half the die area used. Still, I'd assume that per CCD, they'll run the same overall power limit, so average power density is same. If core power density increases or decreases depends on the relative change in core to cache ratio.

Cache is the least dense part of the CCD by a lot, so the power/energy density for the CCD does go up if you decrease the cache and locate the cores closer to each other, doubling the amount or not. Assuming you make use of that area reeducation and don't leave it as blank silicon.

 

I don't think it's half, Zen4c/Beragmo is 16 cores per CCD rather than 8 cores per CCD but I don't think the CCDs are the same physical dimensions, I could look before posting but.... don't want to 

[porina]

2 hours ago, RejZoR said:

I wonder how would top end Threadripper with 384MB of L3 cache fare in games if you cut down the threads by disabling cores in BIOS to keep its clocks higher. That would be like 3x the X3D models cache. Would be interesting to see if games scale beyond the X3D cache capacities or not.

Probably not well. The cache would be split across several different CCD, so you'd get something like 7950X vs 7800X but possibly much worse. This is a (paper) problem I have with AMD's approach. You ideally need to think of each CCD as its own thing. Intel's way is far more unified.

 

2 hours ago, leadeater said:

8 channels is obviously better but maybe not if the motherboard cost is say double that of the TR platform.

We have to wait and see on the mobo pricing. On Intel's side, the few I looked up around launch had both tiers so close together in pricing, if you can consider the lower one, the stretch to the higher one wasn't significant. See it like 7900 XT vs XTX, or 4090 vs 4080.

 

2 hours ago, leadeater said:

I would probably go with a w5-2455X, 4 channel is fine and actually more PCIe lanes than the TR platform.

TR has 80 lanes, but fewer of them are 5.0 compared to Intel. So it depends if you want 5.0 lanes, or just any lanes. I think for most people, the 4.0 lanes would be just fine.

 

2 hours ago, leadeater said:

I could look before posting but.... don't want to 

I know that problem very well

[RejZoR]

Right, I forgot so many cores will be across several CCD's that all have own L3...

[leadeater]

24 minutes ago, porina said:

TR has 80 lanes, but fewer of them are 5.0 compared to Intel. So it depends if you want 5.0 lanes, or just any lanes. I think for most people, the 4.0 lanes would be just fine.

Ahh I may have missed that detail haha. Not sure it would change much for me though. I have a feeling the Intel option I'd be looking at would be cheaper than any equivalent AMD option, which would have higher performance too outside of AVX512.

 

 

[GOTSpectrum]

3 hours ago, leadeater said:

Cache is the least dense part of the CCD by a lot, so the power/energy density for the CCD does go up if you decrease the cache and locate the cores closer to each other, doubling the amount or not. Assuming you make use of that area reeducation and don't leave it as blank silicon.

 

I don't think it's half, Zen4c/Beragmo is 16 cores per CCD rather than 8 cores per CCD but I don't think the CCDs are the same physical dimensions, I could look before posting but.... don't want to 

it's close to half with a die area (per-core) of just 2.48 mm², compared to 3.84 mm² for Zen4. The actual core is 50% smaller than the core of Zen4 if you are not looking at the cache part included, but the cache as you said just doesn't shrink too well. 

[WereCat]

16 hours ago, porina said:

I think we agree on the technical side but differ in what we call "full fat". For example, the laptop I'm using right now has a 5800H, which is an 8 core Zen 3 APU but with half the L3 of the full configuration 8 core desktop offerings. I view c cores in the same way. It is cut down. It is not full fat from not having that extra cache.

 

Now you got me thinking of what to call the 3D models. Extra fat?  

There is a shot of a Phoenix 2 APU that has both Zen 4 and Zen 4c cores (two Zen 4 and four Zen 4c). The cores are exactly the same but the Zen 4c are a lot smaller (rearranged layout to make it more dense and efficient).

Lower density allows for higher clock speeds than higher density due to less concentrated heat and possibly lower noise.